• Journal of Communications and Networks
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• 제13권3호
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• pp.205-210
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• 2011

This paper presents an approach to the construction of multiple-rate quasi-cyclic low-density parity-check (LDPC) codes. Parity-check matrices of the proposed codes consist of $q{\times}q$ square submatrices. The block rows and block columns of the parity-check matrix correspond to the hyperplanes (${\mu}$-fiats) and points in Euclidean geometries, respectively. By decomposing the ${\mu}$-fiats, we obtain LDPC codes of different code rates and a constant code length. The code performance is investigated in term of the bit error rate and compared with those of LDPC codes given in IEEE standards. Simulation results show that our codes perform very well and have low error floors over the additive white Gaussian noise channel.

• 한국통신학회논문지
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• 제25권1B호
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• pp.201-208
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• 2000

시분할 멀티플렉서는 여러 병렬 스트림(stream)들을 높은 비트율을 갖는 하나의 직렬 스트림으로 결합하는 장치로, 광통신 시스템의 송신부에 사용된다. 본 논문에서는 에미터 크기가 2$\times$8um\sup 2\인 SiGe HBT를 사용하여 4:1 (4채널) 시분할 멀티플렉서를 설계하였다. 설계된 회로의 동작속도는 10Gbps, 입력전압 및 출력전압은 각각 400mVp-p와 800mVp-p, 20-80% 간의 상승시간 및 하강시간은 각각 34ps와 34ps이며, 전력소모는 1.50W이다.

• 대한전기학회논문지
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• 제38권10호
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• pp.795-804
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• 1989

A parallel analog-to digital converter with neuron-like elements is designed and optically implemented. Its operation principle is based on the simultaneous estimation of bit values for a given analog input. The architecture of the proposed analog-to-digital converter is simpler than that of an earlier one designed by the energy minimization technique, and its digital output is independent of the initial state. Mixed binary-to-full binary converters are also designed by using out analog-to-digital converters as basic computing elements. These converters have simple structures and fast conversion times compared with earlier ones.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -3
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• pp.2071-2074
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• 2002

This paper introduces an encoder design method of Turbo TCM (Trellis Coded Modulation) with symbol puncturing. TTCM consists of two simple trellis codes in parallel and modulator. To obtain an good encoder, we calculate the free distance by the assumption that the punctured symbol is transmitted from the subset that consist of signals with the same systematic bit at random. We develop a search program to find the component encoder which maximize the free distance. Especially, for 8-PSK with code rate 2/3, we search for the component codes. We find a new encoder which has better BER performance than that of Robertson′s encoder. We verify the results through the simulation."

• 한국통신학회논문지
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• 제27권3B호
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• pp.237-243
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• 2002

본 논문에서는 다단계 간섭제거 기법을 적용한 UTRA TDD 모드에서의 채널 추정 기법들의 성능을 다중경로 페이딩 채널 환경에서의 모의 실험을 통해 확인하였다. 또한, UTRA TDD 모드의 장점을 유지할 수 있는 효율적인 Interpolation 기법을 제안하였다. 모의 실험을 수행하여 제안된 기법을 통해 완벽한 채널 추정 조건에서의 다단계 간섭제거 기법의 성능을 얻을 수 있음을 검증하였고. 주어진 BER에서 요구되는 Eb/No를 줄일 수 있음을 확인하였다.

• Journal of Electrical Engineering and information Science
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• 제2권6호
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• pp.74-81
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• 1997

Xcent-Net is a new system network designed to support a clustered SMP called SPAX(Scalable Parallel Architecture based on Xbar) that is being developed by ETRI. It is a duplicated hierarchical crossbar network to provide the connections among 16 clusters of 128 nodes. Xcent-Net is designed as a packet switched, virtual cut-through routed, point-to-point network. Variable length packets contain up to 64 bytes of data. The packets are transmitted via full duplexed, 32-bit wide channels using source synchronous transmission technique. Its plesiochronous clocking scheme eliminates the global clock distribution problem. Two level priority-based round-robin scheme is adopted to resolve the traffic congestion. Clear-to-send mechanism is used as a packet level flow control scheme. Most of functions are built in Xcent router, which is implemented as an ASIC. This paper describes the architecture and the functional features of Xcent-Net and discusses its implementation.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(1)
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• pp.125-128
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• 2002

This paper is about a high-speed MAC (multiplier and accumulator) design applying radix-4 and radix-8 Booth's algorithm at the same time. The optimized hybrid radix design for high speed MAC has taken advantage of both a radix-4 and a radix-8 architectures. A radix-4 architecture meets high-speed, but it takes much more power and chip area than a radix-8 architecture. A radix-8 architecture needs less power and chip area than the other, but it has a bottleneck of generating three times the multiplicand problem. An optimized hybrid architecture performs tile radix-4 multiplication partially in parallel with the generation of three times the multiplicand for use of tile radix-8 multiplication. It reduces the concerned bit width of multiplier in radix-8 multiplication.

• 전자공학회논문지SC
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• 제47권1호
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• pp.42-46
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• 2010

정보보안을 위한 암호화는 종종 Galois Field 상에서 산술 연산의 형태로 이루어진다. 본 논문은 Galois Field 상에서 산술 정보의 지수 연산 처리를 효과적으로 수행하는 방법을 제안한다. 특히 기존의 비트별 병렬 처리 지수 연산기에서 게이트 카운트가 큰 요소를 제거하고, 시스템 상수를 효과적으로 사용하도록 개량함으로써, m 값이 큰 경우에도 고성능인 VLSI 시스템을 설계한다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2007년도 하계종합학술대회 논문집
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• pp.481-482
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• 2007

This paper demonstrates OFDM with adaptive modulation applied to Multiple-Input Multiple-Output (MIMO) systems. We apply an optimization algorithm to obtain a bit and power allocation for each subcarrier assuming instantaneous channel knowledge. The analysis and simulation is considered in two stages. The first stage involves the application of a variable-rate variable-power MQAM technique for a Single-Input Single-Output(SISO) OFDM system. This is compared with the performance of fixed OFDM transmission where a constant rate is applied to each subcarrier. The second stage applies adaptive modulation to a general MIMO system by making use of the Singular Value Decomposition to separate the MIMO channel into parallel subchannels. For a two-input antenna, two-output antenna system, the performance is compared with the performance of a system using selection diversity at the transmitter and maximal ratio combining at the receiver.

• 전자공학회논문지C
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• 제34C권6호
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• pp.22-27
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• 1997

This paper propose a novel VLSI architecture for a multiplierless FIR filter chip providing variable-length taps. To change the number of taps, we propose two special features called a data-reuse structure and a recurrent-coefficient scheme. These features consist of several MUXs and registers and reduce the number of gates over 20% compared with existing chips using an address generation unit and a modulo unit. Since multipliers occupy large VLSI area, a multiplierless filter chip meeting real-time requirement can save large area. We propose a modified bit-serial multiplication algorithm to compute two partial products in parallel, and thus, the proposed filter is twice faster and has smaller hardware than previous multiplierless filters. We developed VHDL models and performed logic synthesis using the 0.8.mu.m SOG (sea-of-gate) cell library. The chip has only 9,507 gates, was fabricated, and is running at 77MHz.