• International journal of advanced smart convergence
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• 제11권4호
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• pp.96-103
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• 2022

This paper presents the analysis of increasing the resolution of True-Time-Delay (TTD) by 0.5-bit for phased-array antenna system which is one of the Multiple-Input and Multiple Output (MIMO) technologies. For the analysis, a 5.5-bit True-Time Delay (TTD) integrated circuit is designed and analyzed in terms of beam steering performance. In order to increase the number of effective bits, the designed 5.5-bit TTD uses Single Pole Triple Throw (SP3T) and Double Pole Triple Throw (DP3T) switches, and this method can minimize the circuit area by inserting the minimum time delay of 0.5-bit. Furthermore, the circuit mostly maintains the performance of the circuit with the fully added bits. The idea of adding 0.5-bit is verified by analyzing the relation between the number of bits and array elements. The 5.5-bit TTD is designed using 0.18 ㎛ RF CMOS process and the estimated size of the designed circuit excluding the pad is 0.57×1.53 mm². In contrast to the conventional phase shifter which has distortion of scanning angle known as beam squint phenomenon, the proposed TTD circuit has constant time delays for all states across a wide frequency range of 4 - 20 GHz with minimized power consumption. The minimum time delay is designed to have 1.1 ps and 2.2 ps for the 0.5-bit option and the normal 1-bit option, respectively. A simulation for beam patterns where the 10 phased-array antenna is assumed at 10 GHz confirms that the 0.5-bit concept suppresses the pointing error and the relative power error by up to 1.5 degrees and 80 mW, respectively, compared to the conventional 5-bit TTD circuit.

• 한국산업정보학회논문지
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• 제20권1호
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• pp.1-7
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• 2015

In this paper, a 12-bit high resolution, power and area efficiency hybrid digital pulse width modulator (DPWM) with process and temperature (PT) calibration has been proposed for digital controlled DC-DC converters. The hybrid structure of DPWM combines a 6-bit differential tapped delay line ring-mux digital-to-time converter (DTC) schema and a 6-bit counter-comparator DTC schema, resulting in a power and area saving solution. Furthermore, since the 6-bit differential delay line ring oscillator serves as the clock to the high 6-bit counter-comparator DTC, a high frequency clock is eliminated, and the power is significantly saved. In order to have a simple delay cell and flexible delay time controllability, a voltage controlled inverter is adopted to build the deferential delay cell, which allows fine-tuning of the delay time. The PT calibration circuit is composed of process and temperature monitors, two 2-bit flash ADCs and a lookup table. The monitor circuits sense the PT (Process and Temperature) variations, and the flash ADC converts the data into a digital code. The complete circuits design has been verified under different corners of CMOS 0.18um process technology node.

• 한국인터넷방송통신학회논문지
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• 제10권6호
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• pp.119-123
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• 2010

마크-젠더 변조기와 광 간섭계를 이용한 10Gb/s 광 듀오바이너리 송신기의 전송 성능을 고찰하였다. 전송 거리를 증가시키기 위해서 전송 시스템이 받는 영향을 변조기의 구동 전압비와 광 간섭계의 시간 지연 관점에서 컴퓨터 모의실험을 통하여 이론적 분석을 하였다. 구동 전압비를 줄이고 부분 비트 시간 지연을 최적화하여 보다 향상된 전송 성능을 확인하였다.

• 한국통신학회논문지
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• 제22권11호
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• pp.2401-2408
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• 1997

The measured pulse shapes provided in the given data package demonstrated pulse distortions due to laser speckle. the distorted pulse shapes were carefully analyzed, modeled, and then applied to the DTTL(Digital-data Transition Tracking Loop)[1] bit synchronizer simulator to measure the mean time delay and its delay variation performance. The result showed that the maximum mean time delay variation with the modeled data was 12.5% when window size equals 1. All the data given were located within this modeled boundary and the maximum eman time delay variation was 7% in this case. The mean time delay variation was known to be smaller by reducing the window size [2][5][6]. The mitigated delay variation was 2.5% in the modeled case and 1.4% in the data set given when the windown size equals 0.1. With the digital DTTL insteal of analog DTTL, similar results was obtained.

• 한국전자파학회논문지
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• 제28권11호
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• pp.924-927
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• 2017

본 논문에서는 6~18 GHz 대역 8-비트 true time delay(TTD) 회로의 설계 및 측정결과에 대하여 기술하였다. 단위 지연 회로는 상대적으로 시간 지연 변화율이 일정한 m-유도 필터(m-derived filter)를 이용하였다. 설계한 8-비트 TTD는 2개의 single-pole double-throw(SPDT)와 7개의 double-pole double-throw(DPDT) 스위치로 구현하였으며, 인덕터를 이용하여 반사 특성을 개선하였다. 설계된 8-비트 TTD는 $0.18{\mu}m$ CMOS 공정을 이용하여 제작하였다. 측정된 TTD 회로의 시간 가변 범위는 250 ps이고, 시간 지연 해상도는 약 1 ps이다. 6~18 GHz의 동작 주파수에서 RMS 시간 지연 오차는 11 ps 미만이며, 입출력 반사 손실은 10 dB 이상이다. 공급 전압은 1.8 V이며, 소비 전력은 0.0 mW이다. 칩 면적은 $2.36{\times}1.04mm^2$이다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권3호
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• pp.193-197
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• 2013

This paper presents a 5-bit true time delay circuit using a standard 0.18 ${\mu}m$ CMOS process for the broadband phased array antenna without the beam squint. The maximum time delay of ~106 ps with the delay step of ~3.3 ps is achieved at 5-20 GHz. The RMS group delay and amplitude errors are < 1 ps and <2 dB, respectively. The measured insertion loss is <27 dB and the input and output return losses are <12 dB at 5-15 GHz. The current consumption is nearly zero with 1.8 V supply. The chip size is $1.04{\times}0.85\;mm^2$ including pads.

• 전기전자학회논문지
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• 제20권2호
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• pp.167-170
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• 2016

정적 램의 비트라인을 정밀하게 추적하는 감지증폭기의 enable 신호를 만들기 위해 replica bit-line 기술 (RBL)이 사용된다. 하지만, 공정으로 인한 문턱전압의 변화는 replica bit-line 회로에 흐르는 전류를 변화시키고 이는 감지증폭기의 enable 신호 생성 시간 ($T_{SAE}$)을 변화시키며, 결과적으로는 읽기 동작을 불안정하게 한다. 본 논문에서는 conventional replica bit-line delay ($RBL_{conv}$)구조 및 $T_{SAE}$ 변화를 감소시킬 수 있는 개선 구조인 dual replica bit-line delay (DRBD)구조와 multi-stage dual replica bit-line delay(MDRBD)구조를 소개하고, 14nm FinFET 공정, 동작전압 0.6V에서 각 기술들에 대한 읽기 성공률이 $6{\sigma}$를 만족하는 최대 on-cell 개수를 simulation을 통해 찾고 이때 각 구조에 대한 performance와 에너지를 비교했다. 그 결과, $RBL_{conv}$ 대비 DRBD와 MDRBD의 performance는 각각 24.4%와 48.3% 저하되고 에너지 소모는 각각 8%와 32.4% 감소된 것을 관찰하였다.

• 한국산업정보학회논문지
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• 제20권6호
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• pp.21-27
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• 2015

본 논문은 리눅스 환경에서 9비트 RS-232 통신에 필요한 패러티 모드 전환 방식을 사용할 때 발생하는 바이트 간 전송 지연증가 문제를 분석하고 해결책을 제시한다. 문자 전송방식인 RS-232통신에서 메시지의 시작을 나타내기 위하여 9비트통신을 하는 경우가 상당히 있다. 8 비트 문자통신을 기본으로 하는 통상의 리눅스에서는 9비트지원을 하기위해서는 패러티 모드를 변환하는 방법이 사용되는데, 실험결과 이때 OS 틱(tick) 수준의 지연이 발생하는 것을 확인하였다. 본 논문에서 지연의 원인이 드라이버에서 전송 FIFO 버퍼에 남은 데이터를 기다리는데 걸리는 시간의 최소단위를 OS 틱을 사용하기 때문인 것을 밝혀내었으며, 표준 리눅스 드라이버를 수정하여 패러티 모드전환 시간을 1ms 이내로 감소시켰다. 최근 다양한 시스템 통신 방식의 개발되었지만, 여전히 기존의 많은 표준 및 시스템이 RS-232 방식을 사용하여 9 bit 통신을 하고 잇는 경우에 리눅스 활용이 가능하게 되었다는 의미가 있다.

• Progress in Superconductivity
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• 제9권2호
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• pp.157-161
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• 2008

Due to high speed operations and ultra low power consumptions RSFQ logic circuit is a very good candidate for future electronic device. The focus of the RSFQ circuit development has been on the advancement of analog-to-digital converters and microprocessors. Recent works on RSFQ ALU development showed the successful operation of an 1-bit block of ALU at 40 GHz. Recently, the study of an RSFQ analog-to-digital converter has been extended to the development of a single chip RF digital receiver. Compared to the voltage logic circuits, RSFQ circuits operate based on the pulse logic. This naturally leads the circuit structure of RSFQ circuit to be pipelined. Delay time on each pipelined stage determines the ultimate operating speed of the circuit. In simulations, a two junction Josephson transmission line's delay time was about 10 ps, a splitter's 14.5 ps, a switch's 13 ps, a half adder's 67 ps. Optimization of the 4-bit ALU circuit has been made with delay time consideration to operate comfortably at 10 GHz or above.

• ETRI Journal
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• 제40권6호
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• pp.693-698
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• 2018

This paper presents a true-time delay (TTD) using a commercial $0.13-{\mu}m$ CMOS process for wideband phased-array antennas without the beam squint. The proposed TTD consists of four wideband distributed gain amplifiers (WDGAs), a 7-bit TTD circuit, and a 6-bit digital step attenuator (DSA) circuit. The T-type attenuator with a low-pass filter and the WDGAs are implemented for a low insertion loss error between the reference and time-delay states, and has a flat gain performance. The overall gain and return losses are >7 dB and >10 dB, respectively, at 2 GHz-18 GHz. The maximum time delay of 198 ps with a 1.56-ps step and the maximum attenuation of 31.5 dB with a 0.5-dB step are achieved at 2 GHz-18 GHz. The RMS time-delay and amplitude errors are <3 ps and <1 dB, respectively, at 2 GHz-18 GHz. An output P1 dB of <-0.5 dBm is achieved at 2 GHz-18 GHz. The chip size is $3.3{\times}1.6mm^2$, including pads, and the DC power consumption is 370 mW for a 3.3-V supply voltage.