• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.1
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• pp.20-30
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• 2001

A 1.8V $650{\;}\textrm{mm}^2$ 4Gb DRAM having $0.10{\;}\mu\textrm{m}^2$ cell size has been successfully developed using 0.11 $\mu\textrm{m}$DRAM technology. Considering manufactur-ability, we have focused on developing patterning technology using KrF lithography that makes $0.11{\;}\mu\textrm{m}$ DRAM technology possible. Furthermore, we developed novel DRAM technologies, which will have strong influence on the future DRAM integration. These are novel oxide gap-filling, W-bit line with stud contact for borderless metal contact, line-type storage node self-aligned contact (SAC), mechanically stable metal-insulator-silicon (MIS) capacitor and CVD Al process for metal inter-connections. In addition, 80 nm array transistor and sub-80 nm memory cell contact are also developed for high functional yield as well as chip performance. Many issues which large sized chip often faces are solved by novel design approaches such as skew minimizing technique, gain control pre-sensing scheme and bit line calibration scheme.

• Proceedings of the Korea Information Processing Society Conference
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• 2006.05a
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• pp.1151-1154
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• 2006

다양한 무선 네트워킹의 출현은 유무선 혼합형태의 네트워크 망으로 변화되면서 기존의 유선 중심의 네트워크 기반으로 구현된 TCP에 많은 문제점을 가져왔다. 높은 비트오류율, 낮은 대역폭 그리고 높은 지연 등은 TCP/IP 통신을 효율적으로 지원하지 못하는 원인이 된다. 또한 BS(Base Station:기지국)에서 보낸 패킷이 MH(Mobile Node : 이동성을 갖는 노드)가 수신범위 밖으로 벗어나면서 손실로 이어질 경우 성능 저하의 원인이 되기도 한다. 본 논문에서는 MN의 ACK에 수신신호 관련 flag bit를 추가하면서 BS에서 추가된 ACK의 flag bit를 이용해서 패킷손실을 최소화하는 기법을 제안한다.

• Journal of Communications and Networks
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• v.12 no.6
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• pp.616-623
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• 2010

In this paper, exact closed-form expressions for outage probability and bit error probability (BEP) are presented for multi-hop decode-and-forward (DF) relaying schemes in conjunction with cooperative diversity, in which selection combining technique is employed at each node. We have shown that the proposed protocol offers remarkable diversity advantage over direct transmission as well as the conventional DF relaying schemes with the same combining technique. We then investigate the system performance when different diversity schemes are employed. It has been observed that the system performance loss due to selection combining relative to maximal ratio combining is not significant. Simulations are performed to confirm our theoretical analysis.

• Proceedings of the Optical Society of Korea Conference
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• 1989.02a
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• pp.85-88
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• 1989

Introducing and optimizing it-significance to the Hopfield model, ten highly correlated binary images, i.e., numbers "0" to "9", are successfully stored and retrieved in a 6x8 node system. Unlike many other neural networks models, this model has stronger error correction capability for correlated images such as "6", "8", "3", and "9". the bit-significance optimization is regarded as an adaptive learning process based on least-mean-square error algorithm, and may be implemented with another neural nets optimizer. A design for electro-optic implementation including the adaptive optimization networks is also introduced.uding the adaptive optimization networks is also introduced.

• Journal of IKEEE
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• v.16 no.3
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• pp.265-273
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• 2012

Data stability and leakage power dissipation have become a critical issue in scaled SRAM design. In this paper, an advanced 8T SRAM cell improving the read and write stability of data storage elements as well as reducing the leakage current in the idle mode is presented. During the read operation, the bit-cell keeps the noise-vulnerable data 'low' node voltage close to the ground level, and thus producing near-ideal voltage transfer characteristics essential for robust read functionality. In the write operation, a negative bias on the cell facilitates to change the contents of the bit. Unlike the conventional 6T cell, there is no conflicting read and write requirement on sizing the transistors. In the standby mode, the built-in stacked device in the 8T cell reduces the leakage current significantly. The 8T SRAM cell implemented in a 130 nm CMOS technology demonstrates almost 100 % higher read stability while bearing 20 % better write-ability at 1.2 V typical condition, and a reduction by 45 % in leakage power consumption compared to the standard 6T cell. The stability enhancement and leakage power reduction provided with the proposed bit-cell are confirmed under process, voltage and temperature variations.

• Journal of Korea Multimedia Society
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• v.13 no.6
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• pp.901-910
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• 2010

$IP^2$, as an extended concept of the next generation IMT network, is a concept of basically supporting mobility using two steps of IP address (i.e. IPha (IP Host address) and IPra (IP routing address)) in IP backbone network. Current $IP^2$system has a shortcoming of excess usage of network resources caused by sending paging messages to all cells in LA (Location Area) in paging procedure. Considering the evolving direction of network, which is taking mobility with various speed and integration of devices into consideration, this shortcoming must be overcome. In this paper, we proposed a method to reduce time and memory for paging by maintaining current information of MN (Mobile Node) not in Active state with proxy server. Performance evaluation based on NS-2 simulations has shown that the efficiency of network resources is improved in the proposed method.

• Journal of Korea Multimedia Society
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• v.4 no.5
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• pp.390-395
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• 2001

In this paper, we propose a fast warping prediction using bit-pattern for motion estimation. Because of the spatial dependency between motion vectors of neighboring node points carrying motion information, the optimization of motion search requires an iterative search. The computational load stemming from the iterative search is one of the major obstacles for practical usage of warping prediction. The motion estimation in the proposed algorithm measures whether the motion content of the area is or not, using bit-pattern. Warping prediction using the motion content of the area make the procedure of motion estimation efficient by eliminating an unnecessary searching. Experimental results show that the proposed algorithm can reduce more 75% iterative search while maintaining performances as close as the conventional warping prediction.

• ETRI Journal
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• v.43 no.3
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• pp.389-399
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• 2021

In this paper, we propose one-bit feedback-based distributed beamforming (DBF) techniques for simultaneous wireless information and power transfer in interference channels where the information transfer and power transfer networks coexist in the same frequency spectrum band. In a power transfer network, multiple distributed energy transmission nodes transmit their energy signals to a single energy receiving node capable of harvesting wireless radio frequency energy. Here, by considering the Internet-of-Things sensor network, the energy harvesting/information decoding receivers (ERx/IRx) can report their status (which may include the received signal strength, interference, and channel state information) through one-bit feedback channels. To maximize the amount of energy transferred to the ERx and simultaneously minimize the interference to the IRx, we developed a DBF technique based on one-bit feedback from the ERx/IRx without sharing the information among distributed transmit nodes. Finally, the proposed DBF algorithm in the interference channel is verified through the simulations and also implemented in real time by using GNU radio and universal software radio peripheral.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.11
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• pp.1-11
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• 1997

The transient current components of the dRAM are analyzed and the sensing current, data path operation current and DC leakage current are revealed to be the major curretn components. It is expected that the supply voltage of less than 1.5V with low VT MOS witll be used in multi-giga bit dRAM. A low voltage dual VT self-timed CMOS logic in which the subthreshold leakage current path is blocked by a large high-VT MOS is proposed. An active signal at each node of the nature speeds up the signal propagation and enables the synchronous DRAM to adopt a fast pipelining scheme. The sensing current can be reduced by adopting 8 bit prefetch scheme with 1.2V VDD. Although the total cycle time for the sequential 8 bit read is the same as that of the 3.3V conventional DRAM, the sensing current is loered to 0.7mA or less than 2.3% of the current of 3.3V conventional DRAM. 4 stage pipeline scheme is used to rduce the power consumption in the 4 giga bit DRAM data path of which length and RC delay amount to 3 cm and 23.3ns, respectively. A simple wave pipeline scheme is used in the data path where 4 sequential data pulses of 5 ns width are concurrently transferred. With the reduction of the supply voltage from 3.3V to 1.2V, the operation current is lowered from 22mA to 2.5mA while the operation speed is enhanced more than 4 times with 6 ns cycle time.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.571-575
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• 2004

Having age of ubiquitous ahead, existing IPv4's address space insufficiency phenomenon appears because of increasing network usage as well as multimedia data transmission becomes much, necessity of new IP address system that guarantee QoS are needed. IPv6 was made to solve these problem. IPv6 solves address space insufficiency phenomenon offering by 128bit address space, and also offers hierarchical address layer that support improved QoS. IPv6 defines relation between surrounding node using Neighbor Discovery protocol. Used Neighbor Discovery messages, grasp surrounding node, include important informations about network. These network information outcrops can give rise in network attack and also service that use network will paralysis. Various kinds of security limitation was found in Present Neighbor Discovery protocol therefore security function to supplement tris problem was required. In this thesis, Secure Neighbor Discovery protocol that add with security function was design and embody by CGA module and SEND module.