• 대한전자공학회논문지TC
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• 제40권10호
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• pp.79-88
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• 2003

링 구조형 광통신망에 적합한 완전 광 패킷 스위칭 시스템을 실험적으로 검증한다. 실험적 검증을 위해, 비디오 신호는 헤더와 페이로드로 구성된 광 패킷에 실리고, 완전 광 패킷 스위칭 노드에 전달된다. 전달된 광 패킷은 여러가지 완전 광 프로세서에 의해 처리되는데, 그들은 완전 팡 헤더 처리기, 패킷-레벨 클럭 추출기, 비트-레벨 클럭 추출기, 데이타 형태 변환기 등으로 구성되어 있다.

• 한국멀티미디어학회논문지
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• 제20권12호
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• pp.1940-1950
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• 2017

The security threat types in underwater communication networks environment are almost the same as the terrestrial, but the security of mechanisms the terrestrial RF-based networks environment can not be directly applied due to not only the limited resources of each node but also unsafe channel such as low propagation delay, high bit error rate etc. Nevertheless there has not been much research on the security of underwater acoustic communication networks. Therefore, in this paper analyzes the differences between the terrestrial communication networks and underwater acoustic communication networks, and identifies issues that are the starting points of underwater communication networks security research.

• Journal of Communications and Networks
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• 제11권6호
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• pp.556-563
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• 2009

A side channel analysis is a very efficient attack against small devices such as smart cards and wireless sensor nodes. In this paper, we propose an efficient key detection method using a peak selection algorithm in order to find the advanced encryption standard secret key from electromagnetic signals. The proposed method is applied to a correlation electromagnetic analysis (CEMA) attack against a wireless sensor node. Our approach results in increase in the correlation coefficient in comparison with the general CEMA. The experimental results show that the proposed method can efficiently and reliably uncover the entire 128-bit key with a small number of traces, whereas some extant methods can reveal only partial subkeys by using a large number of traces in the same conditions.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.705-706
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• 2008

The feature of 6LoWPAN is the capability of the dynamic assignment of 16bit short addresses. By using this dynamically assigned short address, a hierarchical routing is employed. In case of node failure, this hierarchical routing don't support a technique for path recovery. So, this paper proposes the path recovery technique for hierarchical routing over 6LoWPAN.

• ETRI Journal
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• 제18권4호
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• pp.229-244
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• 1997

Realization of the economical, reliable, and efficient ATM interface block becomes an important key to development of the ATM switching system when we consider new issues raised recently. In this paper, we summarize requirements for the ATM interface block and present the UNI (User Network Interface)/NNI (Network Node Interface) architecture to meet these requirements. We also evaluate the performance of the multiplexer adopting the various multiplexing schemes and service disciplines. For ATM UNI/NNI interface technologies, we have developed a new policing device using the priority encoding scheme. It can reduce the decision time for policing significantly. We have also designed a new spacer that can space out the clumped cell stream almost perfectly. This algorithm guarantees more than 99 % conformance to the negotiated peak cell rate. Finally, we propose the interface architecture for accommodation of the ABR (Available Bit Rate) transfer capability. The proposed structure that performs virtual source and virtual destination functions as well as a switch algorithm can efficiently accommodate the ABR service.

• ETRI Journal
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• 제29권4호
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• pp.457-462
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• 2007

This work presents a low-voltage static random access memory (SRAM) technique based on a dual-boosted cell array. For each read/write cycle, the wordline and cell power node of selected SRAM cells are boosted into two different voltage levels. This technique enhances the read static noise margin to a sufficient level without an increase in cell size. It also improves the SRAM circuit speed due to an increase in the cell read-out current. A 0.18 ${\mu}m$ CMOS 256-kbit SRAM macro is fabricated with the proposed technique, which demonstrates 0.8 V operation with 50 MHz while consuming 65 ${\mu}W$/MHz. It also demonstrates an 87% bit error rate reduction while operating with a 43% higher clock frequency compared with that of conventional SRAM.

• 전자공학회논문지B
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• 제32B권12호
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• pp.1652-1662
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• 1995

In this paper, a hybrid neural network is proposed to improve the learning ability of a neural network. The union of the characteristics of a Self-Organizing Neural Network model and of multi-layer perceptron model using the backpropagation learning method gives us the advantage of reduction of the learning error and the learning time. In learning process, the proposed hybrid neural network reduces the number of nodes in hidden layers to reduce the calculation time. And this proposed neural network uses the fuzzy feedback values, when it updates the responding region of each node in the hidden layer. To show the effectiveness of this proposed hybrid neural network, the boolean function(XOR, 3Bit Parity) and the solution of inverse kinematics are used. Finally, this proposed hybrid neural network is applied to the visual tracking control of a PUMA560 robot, and the result data is presented.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제10권12호
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• pp.5361-5374
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• 2016

Combining channel coding and network coding in a physical layer in a fading channel, generalized joint channel-network coding (G-JCNC) is proved to highly perform in a two-way relay channel (TWRC). However, most relevant discussions are restricted to symmetric networks. This paper investigates the G-JCNC protocols in an asymmetric TWRC (A-TWRC). A newly designed encoder used by source nodes that is dedicated to correlate codewords with different orders is presented. Moreover, the capability of a simple common non-binary decoder at a relay node is verified. The effects of a power match under various numbers of iteration and code lengths are also analyzed. The simulation results give the optimum power match ratio and demonstrate that the designed scheme based on G-JCNC in an A-TWRC has excellent bit error rate performance under an appropriate power match ratio.

• 대한전자공학회논문지
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• 제27권1호
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• pp.1-9
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• 1990

This paper investigates the significance and the implication of the pointer scheme, which was recently adapted by CCITT as a standard synchronization method in the broadband network-node interface environment, and discusses the merits of the pointer scheme in comparison with the conventional positive justification method. It also analyzes the jitter performance of the communication system employing the pointer scheme based on the fact that the pointer scheme corresponds to a multiple-bit positive/zero/negative justification.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.561-562
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• 2006

This paper presents an SRAM which uses the technique to equalize the internal cell node by adding an NMOS transistor. Accordingly, the write driver operates rapidly in a differential current of bit lines, and the operation speed of SRAM improves. An SRAM was implemented with a memory cell, a sense amplifier and a write driver. The SRAM obtained the performance of 18% power reduction and improvement of 56% operation speed. And Power delay product was reduced with 63%. The proposed SRAM was designed based on a 0.35um 1P4M CMOS technology.