• Title/Summary/Keyword: Bit extension

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Quality Characteristics and Functionality of Rose Sparkling Wines by Secondary Fermentation (2차 발효 후 로제 스파클링 와인의 품질 특성 및 기능성)

  • Hyerim Shin;YunJeong Lee;On Bit Hwang;Eui Kwang Park;Sungyeol Choi;Dong Kyu Yoon;Hyang-Sik Yoon
    • The Korean Journal of Food And Nutrition
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    • v.36 no.6
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    • pp.425-435
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    • 2023
  • This study investigated quality characteristics and functionality of rose sparkling wine that were manufactured by secondary fermentation after inoculation of yeast strains. The pH of the samples ranged from 3.96 to 4.05 and total acidity ranged from 0.23 to 0.32%. The alcohol contents of wines ranged from 6.4 to 6.6% and the CO2 pressure ranged from 2.0 to 2.6 bar. The brightness of rose wines ranged from 84.72 to 87.36, the redness from 9.28 to 14.15, and the yellowness from 9.50 to 19.20. The hue value of wines ranged from 1.137 to 1.513 and color intensity ranged from 0.724 to 0.882. Aroma analysis identified 14 alcohols, 22 esters, 4 ketones, 4 acids, and 17 miscellaneous compounds. The total tannin contents and total polyphenol contents of wines were 11.28~12.43 mg% and 24.79~28.20 mg%, respectively. The DPPH radical scavenging activity of wines ranged 63.33 to 67.89% and the ABTS radical scavenging activity of wines 82.16~86.06%. The results of this study provide a basis for establishing the brewing process of rose sparkling wines yeast strains.

Quality Characteristics and Functionality of Mozzarella Cheese with Wine Concentrate (와인 농축액을 첨가한 모짜렐라 치즈의 품질 특성 및 기능성)

  • Shin, Hyerim;Hwang, On Bit;Park, Hyejin;Choi, Sungyeol;Park, Eui Kwang;Kim, Min-Ja
    • The Korean Journal of Food And Nutrition
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    • v.34 no.6
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    • pp.641-649
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    • 2021
  • The objective of this study was to evaluate the quality characteristics of mozzarella cheese added wine concentrate. Mozzarella cheese was produced with different additives of wine concentrate which were 0~5%. The pH and the total acidity of the Cheese were analyzed. We also examined the radical scavenging activities for the antioxidant effect of samples and evaluated for their total polyphenol, and total flavonoid contents. The pH of Meoru wine cheese (6.28~6.37) was significantly higher and total acidity tended to decrease compared to that of the control. L* (lightness) of the wine cheese decreased with increasing amounts of wine concentrates whereas a* (redness) tended to increase. In the texture profile analysis, Meoru wine cheese showed higher values of hardness, gumminess, and chewiness. The ABTS radical scavenging activity of Meoru wine cheese showed the highest value when wine concentrate amounts were 2%. The DPPH radical scavenging activity was significantly increased in cheese added with wine concentrate. Total polyphenol contents and total flavonoid contents of Meoru wine cheese tended to increase with increasing amounts of wine concentrate. This research result highlights the positive influence of wine concentrate addition in cheese. Also, these results are expected to impact the experience programs in farm wineries.

Comparison of Dietary Fiber Content according to Heat Treatment of Korean Agricultural Products and Seaweed (국내 농산물 및 해조류의 가열처리에 따른 식이섬유 함량 비교)

  • Ha, Gi Jeong;Park, Bit Na;Kim, Hyeon Young;Kim, Bong Sin;Park, Yeo Ok;Choi, Jae Hyeok;Park, Jin Ju
    • The Korean Journal of Food And Nutrition
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    • v.35 no.4
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    • pp.239-246
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    • 2022
  • In this study, the dietary fiber content of 33 kinds of agricultural products and seaweeds was compared with that of raw products after heat treatment. To verify the total dietary fiber analysis method, the recovery rate was reviewed by measuring the total dietary fiber content for 4 standard certified substances. As a result, the recovery rate of the analysis value for the true value was 98.8%~103.1%, which was judged to be reliable. The total dietary fiber of vegetables ranged between 0.61~5.36 g/100 g for raw vegetables and 0.55~4.84 g/100 g for heat-treated vegetables. Among the 24 kinds of vegetables used in the analanalysis, the total dietary fiber content of heat-treated Korean radish (3.13 g/100 g) was the highest compared to that of raw radish (0.61 g/100 g). The total dietary fiber of beans was between 13.86~29.69 g/100 g for raw beans and 6.72~18.40 g/100 g for heat-treated beans. In particular, the total dietary fiber content of sword beans was the highest in both raw (29.69 g/100 g) and boiled (18.40 g/100 g) beans. The total dietary fiber content of the three types of seaweed was 1.93~4.85 g/100 g in raw seaweed and 0.99~5.72 g/100 g in heat-treated seaweed.

Constrained One-Bit Transform using Extension of Matching error criterion (정합 오차 기준을 확장한 제한된 1비트 변환 알고리즘)

  • Lee, Sang-Gu;Yun, Jang-Hyeok;Jeong, Je-Chang
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 2013.06a
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    • pp.267-269
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    • 2013
  • 본 논문은 제한된 1비트 변환 (Constrained One-Bit Transform : C1BT) 알고리즘의 정합 오차 기준의 동적 범위를 확장하는 알고리즘을 제안하였다. C1BT는 정합 오차 기준으로 SAD (Sum of Absolute Differences)를 사용하지 않고 CNNMP (Constrained Number of Non-Matching Points)를 사용하여 하드웨어 구현을 용이하게 하고 속도를 대폭 향상시켰다. 이는 기존의 움직임 예측 방법인 전역 탐색 알고리즘 (Full Search Algorithm: FSA)과 비교하여 연산량을 크게 줄였으나 움직임 예측의 정확도를 현저히 감소시켰다. 이 점을 개선하기 위해 이 논문에서는 C1BT의 정합 오차 기준을 확장하여 움직임 예측의 정확도를 높이는 알고리즘을 제안하였다. 기존의 C1BT와 제안하는 알고리즘을 비교한 결과에서 제안하는 알고리즘이 기존의 C1BT에 비해 움직임 예측의 정확도의 기준인 PSNR 측면에서 더 우수한 성능을 보였다.

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32-bit MAC Architecture of a RISC Processor for Portable Terminals (휴대단말용 RISC 프로세서의 32비트 MAC 구조)

  • 정갑천;박성모
    • Proceedings of the IEEK Conference
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    • 2000.11b
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    • pp.357-360
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    • 2000
  • In this paper, we designed 32-Hit MAC architecture of a RISC Processor for portable terminals such as cellular telephones, personal digital assistants, notebooks, etc. In order to have minimum area with best performance, the MAC performs 32 by 8 multiplication per cycle, with early termination circuit that enables multiply cycles depend on the value of multiplier. It uses the sign bit of a partial product and two extra bits for sign extension, The MAC is modeled and simulated in RTL using VHDL. The MAC is synthesized using IDEC C-631 Cell library based on 0.6$\mu\textrm{m}$ CMOS 1-Poly 3-metal CMOS technology.

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BGP Extension for Multihoming in IPv6 (IPv6에서 멀티호밍을 위한 BGP 확장)

  • Woo, Jong-Wook;Ryu, Seung-Hyup;Lee, Jai-Yong;Chung, Jae-Hoon;Park, Jung-Soo
    • Proceedings of the Korea Information Processing Society Conference
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    • 2002.11b
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    • pp.1403-1406
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    • 2002
  • 기존의 인터넷 프로토콜 IPv4의 32-bit 주소 field는 미래의 인터넷 관련 제품의 수요 증가에 미치지 못하는 한계성을 내포하고 있다. 따라서, 128-bit 주소 field 를 가진 IPv6 에 관한 연구가 IPv6 포럼을 중심으로 진행되고 있다. 본 논문은 IPv6의 한 관심분야인 멀티호밍 특히 Site Exit 라우터들 간의 멀티호밍 기법에 관해 서술하였다. 또한, IPv4 및 IPv6에서 기존의 Site Exit 라우터들 간에 널리 쓰이는 BGP Routing 알고리즘을 멀티호밍에 적합하도록 수정한 알고리즘을 제안하였다. 그러므로, 이 알고리즘을 통한 Redundancy 와 Load-Sharing의 이점을 살릴 수 있으며 BGP의 수정은 적으므로 기존의 라우터를 어렵지 않게 멀티호밍에 적합하도록 변환 시킬 수 있다.

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Parallel Branch Instruction Extension for Thumb-2 Instruction Set Architecture (Thumb-2 명령어 집합 구조의 병렬 분기 명령어 확장)

  • Kim, Dae-Hwan
    • Journal of the Korea Society of Computer and Information
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    • v.18 no.7
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    • pp.1-10
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    • 2013
  • In this paper, the parallel branch instruction is proposed which executes a branch instruction and the frequently used instruction simultaneously to improve the performance of Thumb-2 instruction set architecture. In the proposed approach, new 32-bit parallel branch instructions are introduced which combine 16-bit branch instruction with each of the frequently used 16-bit LOAD, ADD, MOV, STORE, and SUB instructions, respectively. To provide the encoding space of the new instructions, the register field in less frequently executed instructions is reduced, and the new instructions are encoded by using the saved bits. Experiments show that the proposed approach improves performance by an average of 8.0% when compared to the conventional approach.

A System Development, Performance Assessment, and Service Implementation of ATM-based High-rate Digital Subscriber Line (HDSL) (ATM 기반 HDSL 개발, 동 선로 상의 성능 평가 및 서비스 구현)

  • 양충열
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.23 no.6
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    • pp.1562-1574
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    • 1998
  • We, in this paper, have implemented T1, E1 and fractional E1 HDSL(High-bit-rate digital subscriber line) function over an ATM switching system. The maxi$\mu$ loop lengths for subscriber service and cell loss rates to meet the bit error rate of 10$^{-7}$ at transmission of 2B1Q HDSL data E1 rate over existing telephone copper wires in the presence of the significant impairments such as NEXT(Nearned crosstalk), impulse noise, power line noise and longitudinal over the CSAs environment consisting of 26 gauge and 25 gauge unloaded copper telephone lines has assessed. HDSL will intially be used to serve private-DS1, ISDN-BRA, and DLC feeders, later DS1 extension from optic fiber cable. We also present market provision for the HDSL.

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A New Crossing Structure Based DB-DES Algorithm for Enhancing Encryption Security (암호화 강도 향상을 위한 새로운 교차구조기반의 DB-DES 알고리즘)

  • Lee, Jun-Yong;Kim, Dae-Young
    • Journal of the Korea Society of Computer and Information
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    • v.12 no.2 s.46
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    • pp.63-70
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    • 2007
  • The Data Encryption Standard (DES) is a block cipher that encrypts a 64 bit block of plaintext into a 64 bit block of ciphertext. The DES has been a worldwide standard for 20 years since it was adopted in 1976. strong. But, due to the rapid development of hardware techniques and cryptanalysis, the DES with 64-bit key is considered to be not secure at the present time. Therefore it became necessary to increase the security of DES. The NG-DES(New Generation DES)[1] is an encryption system which upgrades the encryption security of DES by the key extension and the usage of non-linear f function. It extends not only the size of plaintext and ciphertext to 128 bit but also the Fiestel structure used in each round. This structure has a weak point that the change of each bit of plaintext does not affect all bits of ciphertext simultaneously. In this paper, we propose a modified Fiestel structure of DES and thus increased confusion and diffusion by effectively cross-connecting between outputs in a round and inputs in next round.

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Design and Evaluation of 32-Bit RISC-V Processor Using FPGA (FPGA를 이용한 32-Bit RISC-V 프로세서 설계 및 평가)

  • Jang, Sungyeong;Park, Sangwoo;Kwon, Guyun;Suh, Taeweon
    • KIPS Transactions on Computer and Communication Systems
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    • v.11 no.1
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    • pp.1-8
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    • 2022
  • RISC-V is an open-source instruction set architecture which has a simple base structure and can be extensible depending on the purpose. In this paper, we designed a small and low-power 32-bit RISC-V processor to establish the base for research on RISC-V embedded systems. We designed a 2-stage pipelined processor which supports RISC-V base integer instruction set except for FENCE and EBREAK instructions. The processor also supports privileged ISA for trap handling. It used 1895 LUTs and 1195 flip-flops, and consumed 0.001W on Xilinx Zynq-7000 FPGA when synthesized using Vivado Design Suite. GPIO, UART, and timer peripherals are additionally used to compose the system. We verified the operation of the processor on FPGA with FreeRTOS at 16MHz. We used Dhrystone and Coremark benchmarks to measure the performance of the processor. This study aims to provide a low-power, high-efficiency microprocessor for future extension.