• 전자공학회논문지A
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• 제33A권6호
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• pp.239-247
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• 1996

The accuracy of sample-and-hold amplifiers (SHA's) empolying a CMOS process in limited by nonideal factors such as linearity errors of an op amp and feedthrough errors of switches. In this work, after some linearity improvement techniques for an op amp are discussed, three different SHA's for video signal processing are designed, simulated, and compared. The CMOS SHA design techniques with a 12-bit level accuracy are proposed by minimizing cirucit errors based on the simulated results.

• 한국전자통신학회논문지
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• 제14권5호
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• pp.907-916
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• 2019

본 논문은 CNOT 게이트만을 사용해 모든 다중비트플립 오류들로부터 표적큐비트를 완벽하게 보호할 수 있는 새로운 5-큐비트 다중비트플립코드를 제안하였다. 제안한 다중비트플립코드는 기존의 단일비트플립코드에서와 같이 근원오류부에 Hadamard 게이트 쌍들을 임베딩 할 경우에 쉽게 다중위상플립코드로 확장될 수 있다. 본 논문의 다중비트플립코드와 다중위상플립코드는 4 개 보조큐비트들에 의한 상태벡터 오류정보를 공유한다. 이 4-큐비트 상태벡터들은 Pauli X와 Z 정정이 수반되는 모든 다중플립오류들이 특정 근원오류를 공통으로 포함하는 특성을 반영한다. 이 특성을 이용해 본 논문은 Pauli X와 Z 근원오류의 검출과 정정을 단 3개의 CNOT 게이트로 배치 처리함으로써 다중플립 오류정정을 위한 QECC 설계에도 불구하고 저비용 실현이 가능함을 보였다. 본 논문이 제안한 5-큐비트 다중비트플립코드와 다중위상플립코드는 100% 오류정정율과 50% 오류판별율 특성을 보였다. 이 논문에 제시된 모든 QECC는 QCAD 시뮬레이터를 사용해 검증되었다.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2015년도 추계학술대회
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• pp.420-423
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• 2015

이진가중치 전하재분배 DAC는 커패시터를 기반으로 구동하고 커패시터 값에 따라서 데이터 변환을 시킨다. 전하재분배 DAC의 성능을 결정하는 가장 중요한 요소는 정확한 커패시터와 트랜지스터 소자들의 크기와 특성의 보장이다. 그러나 고해상도의 DAC에서는 회로의 레이아웃 설계시의 mismatch와 칩의 공정변화에 의해 다양한 기생소자 성분 발생과 소자특성의 변화를 피하기는 매우 어렵다. 이러한 소자 mismatch는 DAC 각 비트의 해당 아날로그 값에 비선형 오차를 발생시켜 SNDR 성능저하를 가져오게 된다. 본 논문에서는 커패시터 mismatch에 의한 DAC의 데이터 오차를 감지하고 이를 보상하는 방법을 제안한다. 제안된 방법은 2개의 동일한 DAC를 사용한다. 2개의 DAC는 고정된 차이를 가진 2개의 디지털 입력을 사용함으로써 각각 데이터가 변환된다. 비교기는 허용되는 차이 보다 큰 비선형 오차를 찾을 수 있다. 우리가 제안하는 보정 방법은 비교기가 오차를 제거 할 때 까지 DAC의 커패시터 사이즈를 바꾸면서 미세한 조정을 할 수 있다. 시뮬레이션은 12bit 이진가중치 전하재분배 디지털-아날로그 변환기의 커패시터 mismatch 보정과 비선형 오차를 효과적으로 감지하는 방법을 나타낸다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제11권12호
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• pp.6017-6037
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• 2017

In a multi-resolution image encoding system, the image is encoded into a single file as a layer of bit streams, and then it is transmitted layer by layer progressively to reduce the transmission time across a low bandwidth connection. This encoding scheme is also suitable for multiple decoders, each with different capabilities ranging from a handheld device to a PC. In our previous work, we proposed an edge adaptive hierarchical interpolation algorithm for multi-resolution image coding system. In this paper, we enhanced its compression efficiency by adding three major components. First, its prediction accuracy is improved using context adaptive error modeling as a feedback. Second, the conditional probability of prediction errors is sharpened by removing the sign redundancy among local prediction errors by applying sign flipping. Third, the conditional probability is sharpened further by reducing the number of distinct error symbols using error remapping function. Experimental results on benchmark data sets reveal that the enhanced algorithm achieves a better compression bit rate than our previous algorithm and other algorithms. It is shown that compression bit rate is much better for images that are rich in directional edges and textures. The enhanced algorithm also shows better rate-distortion performance and visual quality at the intermediate stages of progressive image transmission.

• 대한전기학회논문지:시스템및제어부문D
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• 제54권4호
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• pp.243-250
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• 2005

Test methodology is diversity by devices and the number of test pattern is tremendous because the digital circuit includes TTL and CMOS family ICs as well as high density devices such as ROM and RAM. Accordingly, the quick and effective test strategy is required to enhance the test productivity. This paper proposes the test strategy which is able to be applied efficiently to the diversity devices on the digital circuit board by analyzing the structure and characteristic of the digital device. Especially, this test strategy detects the faulted digital device or the faulted digital circuit on the digital board using SSA(Serial Signature Analysis) technique based on the polynomial division theory The SSA technique identifies the faults by comparing the reminder from good device with reminder from the tested device. At this time, the reminder is obtained by enforcing the data stream obtained from output pins of the tested device on the LFSR(Linear Feedback Shift Register) representing the characteristic equation. Also, the method to obtain the optimal signature analysis circuit is explained by furnishing the short bit input streams to the long bit input streams to the LFSR having 8, 12, 16, 20bit input/output pins and by analyzing the occurring probability of error which is impossible to detect. Finally, the effectiveness of the proposed test strategy is verified by simulating the stuck at 1 errors or stuck at 0 errors for several devices on typical 8051 digital board.

• ETRI Journal
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• 제27권1호
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• pp.53-63
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• 2005

A compressed video bitstream is sensitive to errors that may severely degrade the reconstructed images even when the bit error rate is small. One approach to combat the impact of such errors is the use of error concealment at the decoder without increasing the bit rate or changing the encoder. For spatial-error concealment, we propose a method featuring edge continuity and texture preservation as well as low computation to reconstruct more visually acceptable images. Aiming at temporal error concealment, we propose a two-step algorithm based on block matching principles in which the assumption of smooth and uniform motion for some adjacent blocks is adopted. As simulation results show, the proposed spatial and temporal methods provide better reconstruction quality for damaged images than other methods.

• Journal of Communications and Networks
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• 제12권6호
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• pp.529-532
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• 2010

Multi-carrier demultiplexer/demodulator (MCDD) in an on-board processing (OBP) satellite used for digital multimedia services has two typical architectures according to the channel demultiplexing procedure: Multistage multi-carrier demultiplexer (M-MCD) or poly-phase fast Fourier transform (PPF). During the channel demultiplexing, phase and quantization errors influence the performance of MCDD; those errors affect the bit error rate (BER) performance of M-MCD and PPF differently. In this paper, we derive the phase error variances that satisfy the condition that M-MCD and PPF have the same signal to noise ratio according to quantization bits, and then, with these results, analyze the BER performances of M-MCD and PPF. The results provided here may be a useful reference for the selection of M-MCD or PPF in designing the MCDD in an OBP satellite communications system.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.255-258
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• 1999

This paper describes a 40-Msample/s 10-bit CMOS folding and interpolating analog-to-digital converter (ADC). A new 2-step architecture is proposed. The proposed architecture is composed of a coarse ADC bloch for the 6bits of MSBs and a fine ADC block for the remaining 4bits. The amplified folding analog signals in the coarse ADC are selectively chosen for the fine ADC. In the fine ADC, the bubble errors of the comparators are corrected by using the BGM(binary-gray-mixed) code[1] and extra two comparators are used to correct underflow and overflow errors. The proposed ADC was simulated using CMOS 0.25${\mu}{\textrm}{m}$ parameters and occupies 1.0mm$\times$1.0mm. The power consumption is 48㎽ at 40MS/s with 2.5-V power supply. The INL is under $\pm$2.0LSB and the DNL. is under $\pm$1.0LSB by Matlab simulations.

• 한국통신학회논문지
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• 제27권11C호
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• pp.1158-1163
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• 2002

In this paper it is focused on the relation between CLR (Cell Loss Ratio) and blocking probability, GoS(Grade of Services) parameters in the wireless ATM (Asynchronous Transfer Mode) access network which consists of access node and wireless channel. Traffic model of wireless ATM access network is based on the cell scale, burst scale and call connection level. The CLR equation due to buffer overflow for wireless access node is derived for CBR (Constant Bit Rate) traffic. The CLR equation due to random bit errors and burst errors for wireless channel is derived. Using the CLR equation for both access node and wireless channel, the CLR equation of wireless ATM access network is derived. The relation between access network CLR and blocking probability is analyzed for CBR traffic.

• 한국방송∙미디어공학회:학술대회논문집
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• 한국방송공학회 1998년도 Proceedings of International Workshop on Advanced Image Technology
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• pp.5-9
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• 1998

In this paper, we propose an error-resilient transmission technique for the H.263 video data stream over wireless networks. The proposed algorithm employs bit rearrangement hierarchically, providing the robust and exact synchronization against the bit errors, without requiring extra redundant information. In addition, we propose the recovery algorithm for the lost or erroneous motion vectors. We implement the encoder and decoder, based on the H.263 standard, and evaluate the proposed algorithm through intensive computer simulation. The experimental results demonstrate that the proposed algorithm yields good image quality, in spite of the channel errors, and prevents the error propagation both in the spatial and the temporal domain efficiently.