• Proceedings of the IEEK Conference
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• 2001.06a
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• pp.309-312
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• 2001

In this paper, we proposed a system for bit stream wireless communication using audio/video infrared transceiver and implemented a circuit. The proposed transmitter system converted bit stream into analog signal format that is similar to NTSC. Then the analog signal can be transmitted by infrared spatial coupler for A/V signals. And the receiver system recover the bit stream by inverse process of transmitter.

• Journal of Korea Multimedia Society
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• v.13 no.1
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• pp.102-110
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• 2010

H.264 SVC(Scalable Video Coding) provides the advantages of low disk storage requirement and high scalability. However, a streaming server or a user terminal has to extract a bit stream from SVC file. This paper proposes a bit stream extraction method which can get the maximum PSNR value while date bit rate does not exceed the available network bandwidth. To do this, this paper obtains the information about extraction points which can get the maximum PSNR value offline and decides the spatial/temporal resolution of a bit stream at run-time. This resolution information along with available network bandwidth is used as the parameters to a bit stream extractor. Through experiment with JSVM reference software, we proved that proposed bit stream extraction method can get a higher PSNR value.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1215-1218
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• 1998

본 논문은 Digital Audio Compression(AC-3) Standard 인 A-52를 기반으로 하였으며 Borland C++3.1 Compiler를 사용하여 AC-3 Decoding Algorithm 구현하였다. Input Stream은 DVD VOB File에서 AC-3 Stream만을 분리하여 사용하며 최종 출력은 16 Bit PCM File이다. AC-3의 Frame구조는 Synchronization Information, Bit Stream Information, Audio Block, Auxiliary Data, Error Check로 구성된다. Aduio Block 은 모두 6개의 Block으로 나뉘어져 있다. BSI와 Side Information을 참조하여 Exponent를 추출하여 Exponent Strategy에 따라 Exponent를 복원한다. 복원된 Exponent 정보를 이용하여 Bit Allocation을 수행하여 각각의 Mantissa에 할당된 Bit수를 계산하고 Stream으로부터 Mantissa를 추출한다. Coupling Parameter를 참조하ㅕ Coupling Channel을 Original Channel로 복원시킨다. Stereo Mode에 대해서는 Rematrixing을 수행한다. Dynamic Range는 Mantissa와 Exponent의 Magnitude를 바꾸는 것으로 선택적으로 사용할 수 있다. Mantissa와 Exponent를 결합하여 Floating Point coefficient로 만든 후 Inverse Transform을 수행하면 PCM Data를 얻을 수 있다. PC에서 듣기 위해서는 Multi Channel을 Stereo나 Mono로 Downmix를 수행한다. 이렇게 만들어진 PCM data는 PCM Data를 재생하는 프로그램으로 재생할 수 있다.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.4
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• pp.753-760
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• 2012

This paper is to show the character coding rule in computer and information equipment etc to improve the transmission efficiency in telecommunications. In the transmission system, the transmission efficiency can be increased by applying the proper character coding method. In datalink layer, HDSL ptotocol use FLAG byte to identify the frame to frame which consists of data bit stream and other control bytes. FLAG byte constits of "01111110". When data bit stream consist of the consecutive 5-bit "1" after "0", the decoder can not distinguish whether the data bit sequence is flag bit stream or data bit stream. To solve the problem, when the line coder in transmitter detects the consecutive 5-bits "1" after "0" in the input data stream, inserts violently the "0" after 5th "1" of the consecutive 5-bit "1" after "0". As a result, when the characters are decoded with the above procedure, the efficiency of system should be decreased. This paper shows the character code rule to minimize the consecutive 5-bits "1" after "0" when the code is given to each characters.

• Journal of Korea Multimedia Society
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• v.14 no.6
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• pp.759-765
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• 2011

In this paper, we proposed fast stream cipher MS64 for use mobile that it is secure, fast, and easy to implement software. The proposed algorithm use the fast operating 213-bit arithmetic shift register(ASR) to generate a binary sequence and produce 64-bit stream cipher by using simple logical operation in non linear transform. MS64 supports 128-bit key in encryption algorithm and satisfy with the safety requirement in modern encryption algorithm. In simulation result shows that MS64 is faster than a 32-bit stream cipher SSC2 in the speed of operation with small usage of memory thus MS64 can be used for mobile devices with fast ciphering.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1355-1359
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• 2004

The two way subscriber transmission systems have tendency to spread its carrier frequency bandwidth or information bit rate and average bit error rate according to popularization of high speed information through the digital communication system, transmission medium and the Internet. This fact is an important incentive to realize new systems. These two way subscriber transmission systems usually use same cable or same carrier frequency bandwidth for up stream channel and down stream channel. In the systems, the disturbances of noise, crosstalk or fading affect the characteristics. Specifically, these disturbances cause the decrease of information bit rate and degradation of transmission quality. This paper proposes the improved method of their degradations using the particular feature of two way subscriber transmission systems and it makes clear proposed method is effective by theoretically and some numerical examples.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.5 no.4
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• pp.321-325
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• 2004

It is quite difficult to create an unbiased and stable random bit stream, as required for statistical randomness, when using a random generator with only a hardware component. In this paper, we studied to reduce the statistical property of the biased bit stream in the output of a real random number generator. The proposed scheme is enhanced the randomness of output bitstream, these test items are used by FIPS 140-1.

• Journal of Institute of Control, Robotics and Systems
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• v.22 no.8
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• pp.671-677
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• 2016

A Controller Area Network (CAN) is a serial communication protocol that is highly reliable and efficient in many aspects, such as wiring cost and space, system flexibility, and network maintenance. Therefore, it is chosen for the communication protocol between a single chip controller based on Field Programmable Gate Array (FPGA) and peripheral devices. In this paper, the design and implementation of CAN IP, which is written in VHSIC Hardware Description Language (VHDL), is presented. The implemented CAN IP is based on the CAN 2.0A specification. The CAN IP consists of three processes: clock generator, bit timing, and bit streaming. The clock generator process generates a time quantum clock. The bit timing process does synchronization, receives bits from the Rx port, and transmits bits to the Tx port. The bit streaming process generates a bit stream, which is made from a message received from a micro controller subsystem, receives a bit stream from the bit timing process, and handles errors depending on the state of the CAN node and CAN message fields. The implemented CAN IP is synthesized and downloaded into SmartFusion FPGA. Simulations using ModelSim and chip test results show that the implemented CAN IP conforms to the CAN 2.0A specification.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.199-202
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• 2003

In this paper, we propose a new 3D coding method for heterogeneous systems over enhanced Access Grid (e-AG) with 3D display using spatio-temporal scalability. The proposed encoder produces four bit-streams: one base layer and enhancement layer l, 2 and 3. The base layer represents a video sequence for left eye with lower spatial resolution. An enhancement layer l provides additional bit-stream needed for reproduction of frames produced in base layer with full resolution. Similarly, the enhancement layer 2 represents a video sequence for right eye with lower spatial resolution and an enhancement layer 3 provides additional bit-stream needed for reproduction of its reference pictures with full resolution. In this system, temporal resolution reduction is obtained by dropping B-frames in the receiver according to network condition. The receiver system can select the spatial and temporal resolution of video sequence with its display condition by properly combining bit-streams.

• Journal of Digital Contents Society
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• v.6 no.3
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• pp.169-174
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• 2005

In this paper we propose efficient design and implementation of JPEG image display board that can display JPEG image on TV. we used NAND Flash Memory to save the compressed JPEG bit stream and video encoder to display the decoded JPEG mage on TV. Also we convert YCbCr to RGB to super impose character on JPEG image. The designed B/D is implemented using FPGA.