• Journal of IKEEE
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• v.20 no.4
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• pp.435-438
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• 2016

HEVC CABAC binary arithmetic decoder operates in three decoding modes i.e. regular, bypass, and termination modes, where their decoding operations and time differ a lot. Furthermore, when renormalization occurs, its internal feedback loop induces large delay. In this paper, a binary arithmetic decoder was designed to solve this problem. In advance, it checks all range values with possible renormalization. When renormalization occurs, it immediately updates range value and finishes all calculation in a cycle. When implemented in 0.18 um process technology, its maximum operating frequency and gate counts are 215 MHz and 5,423 gates, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.1
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• pp.147-156
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• 1998

In this paper, an arithmetic processor using multi-valued logic is designed. For implementing of multi-valued logic circuits, we use current-mode CMOS circuits and design encoder which change binary voltage-mode signals to multi-valued current-mode signals and decoder which change results of arithmetic to binary voltage-mode signals. To reduce the number of partial product we use 4-radix SD number partial product generation algorithm that is an extension of the modified Booth's algorithm. We demonstrate the effectiveness of the proposed arithmetic circuits through SPICE simulation and Hardware emulation using FPGA chip.

• Journal of IKEEE
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• v.20 no.3
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• pp.326-329
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• 2016

HEVC CABAC encoder performs binary arithmetic encoding after syntax elements are converted into binary values. Therefore, in HEVC CABAC decoder, binarized syntax elements from binary arithmetic decoder should be de-binarized into original syntax elements in the de-binarizer. In this paper, a HEVC CABAC de-binarizer architecture was proposed and implemented. It consists of a controller that analyzes and merges binarized syntax elements and an engine that converts merged binarized syntax elements into original syntax elements. The designed de-binarizer was described in Verilog HDL and it was synthesized and verified in 0.18um process technology. Its gate count and maximum operating frequency are 3,114 gates and 220 MHz, respectively.

• Proceedings of the KIEE Conference
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• 2005.07d
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• pp.2967-2969
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• 2005

2003년에 영상압축의 표준으로 제시된 H.264/AVC의 압축성능은 대부분 Context-based Adaptive Binary Arithmetic Codes (CAHAC)라는 새로운 엔트로피 코딩에 기인한 것이다. 그러나, CABAC의 뛰어난 성능에도 불구하고 복잡한 처리과정 때문에 하드웨어로 구현하기가 상당히 곤란하다. 곱셈기가 없는 알고리즘임에도 불구하고 영역(range), 오프셋(offset), 그리고 컨텍스트 변수들(context varivales)을 순차적으로 구해야 하기 때문이다. 이 논문에서는 한번에 최대 두 비트를 디코딩 할 수 있는 예측기법을 통하여 CARAC의 전체적인 디코딩 시간을 줄일 수 있는 방법을 제안한다. 한 비트를 디코딩하기 위해서는 두 개의 심볼(a set of binary symbols)에 대한 확률분포를 사전에 알아야 하지만, 제안된 방법에서는 두 비트를 동시에 디코딩할 수 있도록 네 개의 심볼(two sets of binary symbols)에 대한 확률 분포를 예측하여 디코더에 제공한다. 제안된 예측기법을 CABAC 디코더에 적용한 결과, 기존보다 10-13%의 복호시간을 단축하는 효과를 가졌다. 논문에서 제안된 예측기법을 통한 고속디코더의 구현은 확률을 기반으로 하는 신호처리에 사용되어 고속의 시스템을 구성하는데 효과적으로 적용될 수 있다.

• Journal of IKEEE
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• v.21 no.3
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• pp.280-283
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• 2017

HEVC (high efficiency video coding) exploits CABAC (context-based adaptive binary arithmetic coding) for entropy coding, where a context model estimates the probability for each syntax element. In this paper, a context modeler was designed and implemented for CABAC decoding. lookup table was used to reduce computation and to increase speed. 12 simulations for HEVC standard test sequences and encoder configurations were performed, and the context modeler was verified to perform correction operations. The designed context modeler was synthesized in 0.18um technology. Maximum frequency, maximum throughput, and gate count are 200 MHz, 200 Mbin/s, and 29,268 gates, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.385-390
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• 2013

This paper proposes an efficient hardware architecture of CABAC for HEVC decoder. The proposed method is structured to handle two bins in one cycle, while preserving data dependencies of the CABAC. In addition, the processing time of the proposed architecture is reduced because the operation using Offset and Range is processed while the architecture reads rLPS from rLPSROM. As a result of analyzing operating frequency of the proposed CABAC architecture, the proposed architecture has improved by 40% than the previous one.

• The Transactions of the Korea Information Processing Society
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• v.4 no.7
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• pp.1851-1864
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• 1997

This paper presents an algorithm simplifying the ESOP function by several rules. The algorithm is repeatedly performing operations based on the state of each terms by the product transformation operation of two functions and thus it is simplifying the ESOP function through the reduction of the product terms. Through the minimization of the product terms of the multi-valued input binary multi-output function, an optimization of the input has been done using EXOR PLA with input decoder. The algorithm when applied to four valued arithmetic circuit has been used for a EXOR logic circuit design and the two bits input decoder has been used for a EXOR-PLA design. It has been found from a computer simulation(IBM PC486) that the suggested algorithm can reduce the product terms of the output function remarkably regardless of the number of input variables when the variable AND-EXOR PLA is applied to the poperation circuit.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.3
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• pp.397-409
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• 1993

This paper proposed the design methodology of the 8 bit binary parallel adder with carry book-ahead scheme via current-mode CMOS multivalued logic and simulated the proposed adder under $5{\mu}m$ standard IC process technology. The threshold conditions of $G_K$ and $P_K$ which are needed for m-valued parallel adder with CLA are evaluated and adopted for quaternary logic. The design of quaternary CMOS logic circuits, encoder, decoder, mod-4 adder, $G_K$ and $P_K$ detecting circuit and current-voltage converter is proposed and is simulated to prove the operations. These circuits are necessary for binary arithmetic using multivalued logic. By comparing with the conventional binary adder and the CCD-MVL adder, We show that the proposed adder cab be designed one look-ahead carry generator with 1-level structure under standard CMOS technology and confirm the usefulness of the proposed adder.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.552-555
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• 2007

지상파 DMB등에서 많이 사용하고 있는 기술은 H.264이다. 이 H.264는 적은 비트율에 비하여 고해상도의 영상을 만들어 낸다. 이런 손실압축을 하기 위해서 인트라와 인터등과 같은 전처리 과정과 DCT(Discrete Cosine Transform), 양자화 등등이 존재하지만 H.264에서 실제로 압축이 되는 부분은 엔트로피코딩이다. H.264에서는 Exp-Golomb과 CAVLC(Context-Adaptive Variable Length Coding), CABAC(Context-Adaptive Binary Arithmetic Coding) 세 가지를 지원하고 있다. 이중 CAVLC는 테이블을 기반으로한 압축기법을 사용한다. 테이블을 이용할 때는 코드워드의 길이와 값을 비교하는 방식을 사용하게 된다. 이는 수 많은 메모리 접속으로 인한 전력소모와 연산지연을 가져온다. 본 논문에서는 전송된 비트스트림에서 데이터를 찾을 때 코드워드의 길이와 값을 테이블에 비교해서 찾지 않고 테이블에 존재하는 규칙을 수식화 하여 찾을 수 있도록 하였다. 이는 최초 '1'이 나올때까지의 '0'의 개수와 그 이후 존재하는 코드의 값을 이용하여서 각 단계에 필요한 데이터를 추출해 낸다. 위와 같은 알고리즘을 이용하여 VHDL언어로 설계하였다.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.5
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• pp.155-164
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• 2015

This paper describes a design and implementation of CABAC decoder, which would handle HEVC syntax elements in adaptively pipelined-parallel computation manner. Even though CABAC offers the high compression rate, it is limited in decoding performance due to context-based sequential computation, and strong data dependency between context models, as well as decoding procedure bin by bin. In order to enhance the decoding computation of HEVC CABAC, the flag-type syntax elements are adaptively pipelined by precomputing consecutive flag-type ones; and multi-bin syntax elements are decoded by processing bins in parallel up to three. Further, in order to accelerate Binary Arithmetic Decoder by reducing the critical path delay, the update and renormalization of context modeling are precomputed parallel for the cases of LPS as well as MPS, and then the context modeling renewal is selected by the precedent decoding result. It is simulated that the new HEVC CABAC architecture could achieve the max. performance of 1.01 bins/cycle, which is two times faster with respect to the conventional approach. In ASIC design with 65nm library, the CABAC architecture would handle 224 Mbins/sec, which could decode QFHD HEVC video data in real time.