• International Journal of Fuzzy Logic and Intelligent Systems
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• v.5 no.4
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• pp.327-332
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• 2005

We investigatea new fuzzy-neural networks-Hybrid Fuzzy set based polynomial Neural Networks (HFSPNN). These networks consist of genetically optimized multi-layer with two kinds of heterogeneous neurons thatare fuzzy set based polynomial neurons (FSPNs) and polynomial neurons (PNs). We have developed a comprehensive design methodology to determine the optimal structure of networks dynamically. The augmented genetically optimized HFSPNN (namely gHFSPNN) results in a structurally optimized structure and comes with a higher level of flexibility in comparison to the one we encounter in the conventional HFPNN. The GA-based design procedure being applied at each layer of gHFSPNN leads to the selection leads to the selection of preferred nodes (FSPNs or PNs) available within the HFSPNN. In the sequel, the structural optimization is realized via GAs, whereas the ensuing detailed parametric optimization is carried out in the setting of a standard least square method-based learning. The performance of the gHFSPNN is quantified through experimentation where we use a number of modeling benchmarks synthetic and experimental data already experimented with in fuzzy or neurofuzzy modeling.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.13 no.4
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• pp.171-177
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• 2013

Due to the demand for high speed 3D graphic rendering, video file format conversion, compression, encryption and decryption technologies, the importance of digital signal processor system is growing rapidly. In order to satisfy the real-time constraints, high performance digital signal processor is required. Therefore, as in general purpose computer systems, digital signal processor should be designed as multicore architecture as well. Using UTDSP benchmarks as input, the trace-driven simulation has been performed and analyzed for the 2 to 16-core digital signal processor architectures with the cores from simple RISC to in-order and out-of-order superscalar processors for the various window sizes, extensively.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.2
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• pp.251-256
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• 2017

Recently, multicore processor system is widely adopted not only in general purpose computers but also in embedded systems and mobile devices in order to improve performance. Since the power dissipation issue of multicore processor system is very significant, it must be estimated accurately in the early design stage. In this paper, a fast power analysis tool for a high performance multicore processor based on the trace-driven simulator has been developed. To achieve it, the power dissipation of each hardware unit per core are added. Using SPEC 2000 benchmarks as input, the trace-driven simulation has been performed to estimate the average power dissipation per instruction.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.4
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• pp.169-175
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• 2018

Recently, power dissipation issue is very significant not only in high-end modern processors but also in embedded systems and mobile devices. Based on the power dissipation, hardware and software designers can correctly find the power/performance tradeoffs. Most power analysis tools calculate power dissipation when chip layout or floor planning are finished. In this paper, a trace-driven simulator that can interact with power analysis tool for an embedded microprocessor has been developed. Using MiBench embedded benchmarks as input, the trace-driven simulation has been performed to estimate the average power dissipation which is faster than the conventional tools.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.8
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• pp.84-91
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• 2002

In this paper, we proposed a CLB-based CPLD technology mapping algorithm for power minimization under time constraint in combinational circuit. The main idea of our algorithm is to exploit the "cut enumeration and feasible cluster" technique to generate possible mapping solutions for the sub-circuit rooted at each node. In our technology mapping algorithm conducted a low power by calculating TD and EP of each node and decomposing them on the circuit composed of DAG. It also takes the number of input, output, and OR-term into account on condition that mapping can be done up to the base of CLB, and so it generates the feasible clusters to meet the condition of time constraint. Of the feasible clusters, we should first be mapping the one that h3s the least output for technology mapping of power minimization and choose to map the other to meet the condition of time constraint afterwards. To demonstrate the efficiency of our approach, we applied our algorithm to MCNC benchmarks and compared the results with those of the exiting algorithms. The experimental results show that our approach is shown a decrease of 46.79% compared with DDMAP and that of 24.38% for TEMPLA in the power consumption.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.8B
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• pp.1477-1486
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• 2000

This paper proposes an efficient kernel-based partitioning algorithm for reducing area and power dissipation in combinational circuit design.. The proposed algorithm decreases the power consumption by partitioning a given circuit utilizing a kernel, and reduces the area overhead by minimizing duplicated gates in the partitioned subcircuits. Experimental results for the MCNC benchmarks show that the proposed algorithm is effective by generating circuits consuming 43.6% less power with 30.7% less area on the average, when compared to the previous algorithm based on precomputation circuit structure.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.1C
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• pp.9-17
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• 2005

XML is rapidly spreading as a standard for data representation and exchange, and XML documents are adopted in various applications. According to this trend, researches in database has also focused on efficient storage and retrieval of XML documents. Recently, major (object) relational DBMS vendors support XML functionality, and several native XML DBMSs have been developed in academic or industry side. In addition, various benchmarks have been proposed so as to evaluate these na database performance. In this paper, we evaluate the XBench benchmark using a commercial object-relational DBMS, analyze its performance, and investigate the future improvements of object-relational DBMSs for XML support.

• ETRI Journal
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• v.30 no.4
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• pp.576-586
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• 2008

In most parallel loops of embedded applications, every iteration executes the exact same sequence of instructions while manipulating different data. This fact motivates a new compiler-hardware orchestrated execution framework in which all parallel threads share one fetch unit and one decode unit but have their own execution, memory, and write-back units. This resource sharing enables parallel threads to execute in lockstep with minimal hardware extension and compiler support. Our proposed architecture, called multithreaded lockstep execution processor (MLEP), is a compromise between the single-instruction multiple-data (SIMD) and symmetric multithreading/chip multiprocessor (SMT/CMP) solutions. The proposed approach is more favorable than a typical SIMD execution in terms of degree of parallelism, range of applicability, and code generation, and can save more power and chip area than the SMT/CMP approach without significant performance degradation. For the architecture verification, we extend a commercial 32-bit embedded core AE32000C and synthesize it on Xilinx FPGA. Compared to the original architecture, our approach is 13.5% faster with a 2-way MLEP and 33.7% faster with a 4-way MLEP in EEMBC benchmarks which are automatically parallelized by the Intel compiler.

• Steel and Composite Structures
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• v.20 no.1
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• pp.205-225
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• 2016

In this study the finite element method is utilized to predict the deflection and vibration characteristics of rectangular plates made of saturated porous functionally graded materials (PFGM) within the framework of the third order shear deformation plate theory. Material properties of PFGM plate are supposed to vary continuously along the thickness direction according to the power-law form and the porous plate is assumed of the form where pores are saturated with fluid. Various edge conditions of the plate are analyzed. The governing equations of motion are derived through energy method, using calculus of variations while the finite element model is derived based on the constitutive equation of the porous material. According to the numerical results, it is revealed that the proposed modeling and finite element approach can provide accurate deflection and frequency results of the PFGM plates as compared to the previously published results in literature. The detailed mathematical derivations are presented and numerical investigations are performed while the emphasis is placed on investigating the effect of the several parameters such as porosity volume fraction, material distribution profile, mode number and boundary conditions on the natural frequencies and deflection of the PFGM plates in detail. It is explicitly shown that the deflection and vibration behaviour of porous FGM plates are significantly influenced by these effects. Numerical results are presented to serve as benchmarks for future analyses of FGM plates with porosity phases.

• ETRI Journal
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• v.33 no.5
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• pp.731-740
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• 2011

Reconfigurable computing using a field-programmable gate-array (FPGA) device has become a promising solution in system design because of its power efficiency and design flexibility. To bring the benefit of FPGA to many application programmers, there has been intensive research about automatic translation from high-level programming languages (HLL) such as C and C++ into hardware. However, the large gap of syntaxes and semantics between hardware and software programming makes the translation challenging. In this paper, we introduce a new approach for the translation by using the widely used GCC compiler. By simply adding a hardware description language (HDL) backend to the existing state-of- the-art compiler, we could minimize an effort to implement the translator while supporting full features of HLL in the HLL-to-HDL translation and providing high performance. Our translator, called GCC2Verilog, was implemented as the GCC's cross compiler targeting at FPGAs instead of microprocessor architectures. Our experiment shows that we could achieve a speedup of up to 34 times and 17 times on average with 4-port memory over PICO microprocessor execution in selected EEMBC benchmarks.