• Title/Summary/Keyword: Behavioral logic

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Consumer Adoption of Self-Service Technologies: Integrating the Behavioral Perspective with the Technology Acceptance Model

  • ASHOUR, Mohammed L.;AL-QIREM, Raed M.
    • The Journal of Asian Finance, Economics and Business
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    • v.8 no.3
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    • pp.1361-1369
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    • 2021
  • Recent technological advancements have had a substantial impact on consumer buying behavior. This research aims to determine the factors affecting consumer behavior related to the adoption of self-service technologies (SSTs). The intended findings of this study are expected to contribute to understanding consumer behavior towards the adoption of SSTs taking into account the logic of two main theories in this regard: the Technology Acceptance Model (TAM) and the assumptions of the Behavioral Perspective Model (BPM). This research follows a triangulation approach. Consequently, a number of semi structured interviews were conducted with experts and executive directors from selected SSTs providers in Jordan. In addition, the convenience sampling technique was employed focusing on current (or) previous users of SSTs in the public and private sectors in Jordan using a self-administrative questionnaire (66% response rate). The results confirmed the influence (direct and indirect) of previous experience and personal initiatives and characteristics on consumer intention to use SSTs. In addition, the results indicated the important role of the mediator variables namely: perceived ease of use (EOU), perceived risk (PR), and perceived usefulness (PU) on consumer attitude towards SSTs which in turn will positively affect consumer intention to use SSTs.

VERIFICATION OF PLC PROGRAMS WRITTEN IN FBD WITH VIS

  • Yoo, Jun-Beom;Cha, Sung-Deok;Jee, Eun-Kyung
    • Nuclear Engineering and Technology
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    • v.41 no.1
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    • pp.79-90
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    • 2009
  • Verification of programmable logic controller (PLC) programs written in IEC 61131-3 function block diagram (FBD) is essential in the transition from the use of traditional relay-based analog systems to PLC-based digital systems. This paper describes effective use of the well-known verification tool VIS for automatic verification of behavioral equivalences between successive FBD revisions. We formally defined FBD semantics as a state-transition system, developed semantic-preserving translation rules from FBD to Verilog programs, implemented a software tool to support the process, and conducted a case study on a subset of FBDs for APR-1400 reactor protection system design.

Design and Implementation of the Dual Motor Drive AGV Controller Using CPLD (CPLD를 이용한 이륜 속도차방식 AGV 제어기 설계 및 구현)

  • 진중호;백한석;한석붕
    • Proceedings of the Korea Institute of Convergence Signal Processing
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    • 2000.12a
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    • pp.209-212
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    • 2000
  • This paper describes the design and implementation of a hard- wired AGV controller using CPLD(Complex Programmable Logic Device). The proposed controller manages a guidance equipment, motor and I/O sequence controller for a self-control traveling. Compared with a conventional $\mu$-processor, the CPLD controller using a hard-wired control method can reduce a difficult programming process. Also, the total costs of production are reduced, such as development time, product's size and difficulty because memory, combinational logic and sequential logics are implemented by CPLD. The Controller designed using behavioral description method with VHDL and was synthesized by MAX+Plus II of the ALTERA co. We implemented controller using EPF10K10LC84-4 device.

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64 Bit EISC Processor Design (64 Bit EISC 프로세서 설계)

  • 임종윤;이근택
    • Proceedings of the IEEK Conference
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    • 2000.06b
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    • pp.161-164
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    • 2000
  • The architecture of microprocessor for a embedded system should be one that can perform more tasks with fewer instruction codes. The machine codes that high-level language compiler produces are mainly composed of specific ones, and codes that have small size are more frequently used. Extended Instruction Set Architecture (EISC) was proposed for that reason. We have designed pipe-line system for 64 bit EISC microprocessor. function level simulator was made for verification of design and instruction set architecture was also verified by that simulator. The behavioral function of synthesized logic was verified by comparison with the results of cycle-based simulator.

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Design of the 0-1 Knapsack Processor using VHDL (VHDL을 이용한 0-1 Knapsack 프로세서의 설계)

  • 이재진;송호정;송기용
    • Proceedings of the Korea Institute of Convergence Signal Processing
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    • 2000.08a
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    • pp.341-344
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    • 2000
  • The 0-1 knapsack processor performing dynamic programming is designed and implemented on a programmable logic device. Three types of a processor, each with different behavioral models, are presented, and the operation of a processor of each type is verified with an instance of the 0-1 knapsack problem.

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A Behavioral Scientist's Essay on the Art of Negotiation (협상기예(協商技藝)에 관한 행동과학적(行動科學的) 소고(小考))

  • Baek, Gwang-Gi
    • Korean Business Review
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    • v.11
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    • pp.1-14
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    • 1998
  • In this paper the negotiation skills, which have been so far known as non-scientific or artistic field, are analyzed on the basis of behavioral science view point. Negotiator's behavior and psychological situation are believed to influence the negotiation result significantly, therefore, those factors are reviewed with behavioral science framework. Some concepts developed in Cognitive Psychology to explain the decision making models - prominence, commitment, escalation of commitment, framing, adjustment and anchoring, endowment effect - are reconceptualized and applied to the negotiation skill analysis and negotiation skill development in this paper. As the results of this research, various negotiation skills which have been so far believed as irrational and artistic are now able to be explained on the basis of sound logic and reasoning. This means also that valuable and elegant negotiation skills should be further developed by behavioral scientists.

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Automatic STG Derivation with Consideration of Special Properties of STG-Based Asynchronous Logic Synthesis (신호전이그래프에 기반한 비동기식 논리합성의 고유한 특성을 고려한 신호전이그래프의 자동생성)

  • Kim, Eui-Seok;Lee, Jeong-Gun;Lee, Dong-Ik
    • The KIPS Transactions:PartA
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    • v.9A no.3
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    • pp.351-362
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    • 2002
  • Along with an asynchronous finite state machine, in short AFSM, a signal transition graph, in short STG, is one of the most widely used behavioral description languages for asynchronous controllers. Unfortunately, STGs are not user-friendly, and thus it is very unwieldy and time consuming for system designers to conceive and describe manually the behaviors of a number of asynchronous controllers which constitute an asynchronous control unit for a target system in the form of STGs. In this paper, we suggest an automatic STG derivation method through a process-oriented method. Since the suggested method considers special properties of STG-based asynchronous logic synthesis very carefully, asynchronous controllers which are synthesized from STGs derived through the suggested method are superior in aspects of area, synthesis time, performance and implementability compared to those obtained through previous methods.

Implementation of a 32-Bit RISC Core for Multimedia Portable Terminals (멀티미디어 휴대 단말기용 32 비트 RISC 코어 구현)

  • 정갑천;기용철;박성모
    • Proceedings of the IEEK Conference
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    • 2000.06b
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    • pp.226-229
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    • 2000
  • In this paper, we describe implementation of 32-Bit RISC Core for portable communication/information equipment, such as cellular telephones and personal digital assistants, notebook, etc. The RISC core implements the ARM$\^$R/V4 instruction set on the basis of low power techniques in architecture level and logic level. It operates with 5-stage pipeline, and has harvard architecture to increase execution speed. The processor is modeled and simulated in RTL level using VHDL. Behavioral Cache and MMU are added to the VHDL model for instruction level verification of the processor. The core is implemented using Mentor P'||'&'||'R tools with IDEC C-631 Cell library of 0.6$\mu\textrm{m}$ CMOS 1-poly 3-metal CMOS technology.

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A Study on Model applied to Logic of Systematic Composition on the Space and Shape in Architecture (건축에서 공간형상의 체계적 구성논리를 적용한 모델화에 관한 연구)

  • 이상화
    • Journal of the Korean housing association
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    • v.10 no.2
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    • pp.175-183
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    • 1999
  • This study aims at modeling the compositional method in the architectural space and shape. The composition of space is composed of the position and the area in space. Therefore these elements are established to the functional program applied at the behavioral data. The element of spatial structure is position and scale in space, and the composition of spatial shape is developed repitionally to the combination of build-up method. The functional program is being expertised and the scale in building being lager, the importance of functional program is increased. Applied at data of the functional program at spatial structure, the process is developed to the method of combination. The purpose of this study is approached at the degree of application in modeling on the compositional method in architectural space and shape, which is a fundamental aspect on the quantitative analysis of architectural space.

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A Study on Simulation tracking analysis for Spatial configuration analysis (공간구조분석을 위한 시뮬레이션 추적 분석에 관한 연구)

  • Park, Jong-Hyun;Lee, Jong-Ruyl
    • Journal of The Korean Digital Architecture Interior Association
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    • v.9 no.3
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    • pp.95-102
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    • 2009
  • An architectural space can be considered a life form that interconnects a number of architectural elements such as the humans who live in it. It is difficult to understand and evaluate the complexity of the interrelation between each element, but there have been various attempts to understand and evaluate this architectural space. The Space Syntax that emerged in 1980s has been studied and used more frequently than other methods. Space Syntax is the space analysis tool that analyzes the physical structure of space and represents it as a graph. Space syntax enables its various applications in space analysis by quantifying each spatial property of a whole structure, analyzing it systemically and objectively based on mathematical logic, and representing the results as a quantitative value. Integration of Space Syntax, a widely used index, reflects human behavior in spatial configuration. Meanwhile, there have been various studies in the field of architectural environmental psychology about the relationships between space and human behavior by applying behavioral science to architectural plan. One of the most widely used one is spatial behavior simulation which uses models and simulates the behavioral characteristics to anticipate practical situations and investigate the behavior related spatial problems. In this study, which focuses on the accessibility of the space syntax model, the usefulness of space will be analyzed through the simulation of human behavior that moves through each space. Furthermore, the validity of index will be verified by displaying several examples and compared with integration in space syntax, which represents the usefulness of space.

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