• 한국산업정보학회:학술대회논문집
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• 한국산업정보학회 1998년도 공동추계학술대회 경제위기 극복을 위한 정보기술의 효율적 활용
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• pp.827-834
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• 1998

This paper describes a multi-level simulation technique and its implementation, which accurately solve voltages and currents of circuits descreibed at mixed levels of abstractions. A metho to form a tightly coupled simulation environment is proposed and, starting from a description of a circuit, simulation set-up and analysis procedure of the multi-level simulator for a transient response are presented. Circuit and behavioral simulation techniques and their implementations composing the multi-level simulation are explained in detail. Most of the algorithms implemented in the simulation are based upon the standard simulation techniques in order to obtain the reliability and accuracy of conventinoal simulators. Simulation examples show that the multi-level simulator can analyze circuits containing highly nonlinear behavioral models without loss of accuracy provided the behavioral models are accurate enough.

• 한국정보통신학회논문지
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• 제12권5호
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• pp.893-899
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• 2008

본 논문에서는 C++기반 동작 레벨 회로 시뮬레이션 프로그램인 CPPSIM을 이용하여 전압 조절기와 PLL을 구현하고 시뮬레이션 하였다. 아날로그 회로를 C++코드로 모델링 후 시뮬레이션을 통해 시뮬레이션 툴의 유효성을 살펴보았으며, 아날로그 회로의 단계별 설계와 가능성을 타진하였다. 시뮬레이션 결과 회로의 동작 레벨에서의 설계가능성을 검증할 수 있었다. 또한 PLL을 디지털 신호기반으로 구현하여 아날로그 회로의 디지털화를 시도하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권3호
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• pp.319-329
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• 2016

High-level design aids are mandatory for design of a continuous-time delta-sigma modulator (CTDSM). This paper proposes a top-down methodology design to generate a noise transfer function (NTF) which is compensated for excess loop delay (ELD). This method is applicable to low pass loop-filter topologies. Non-ideal effects including ELD, integrator scaling issue, finite op-amp performance, clock jitter and DAC inaccuracies are explicitly represented in a behavioral simulation of a CTDSM. Mathematical modeling using MATLAB is supplemented with circuit-level simulation using Verilog-A blocks. Behavioral simulation and circuit-level simulation using Verilog-A blocks are used to validate our approach.

• 전자공학회논문지A
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• 제31A권9호
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• pp.146-155
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• 1994

In this paper, we desribe a new system, called BEST, that is used to develop a macromodel or behavioral model easily. It automatically calculates the component values of macromodel represented by equations to satisfy the given specification. Also, it gives the way to analyze both the behavioral model and transistor level circuit, and then compare the analysis results of them to check the correspondence under specific temperature and bias condition, and BEST optimizes the component values of macromodel. Other feature is to characterize MOSFET as switch model which consists of PWL-RC network. Finally, it is possible to generage multi-level netlist which consists of macro/switch/transistor level circuits, and user can determine the trade-off between simulation speed and accuracy. With the graphic user interface form of macromodel development system described above. BEST enable designers to make macromodel by themselves and to uas it. We applied BEST to develop the macromodel for the test circuit and got the 18.6 times simulation speed up with preserving the accuracy within 10% compared to the conventional transistor level circuit simulation. Also, applicability of optimization capability was verified.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.1013-1016
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• 1998

A method for generation of design verification tests from behavior-level VHDL program is presented. Behavioral VHDL programs contain multiple communicating processes, signal assignment statements. So for large, complex system, it is difficult problem to test or simulation. In this paper, we proposed a new hardware design verification method. For this method generates control flow graph(CFG.) and process modeling graph(PMG) in the given under the testing VHDL program. And this method proved very effective that all the assumed design errors could be detected.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.212-215
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• 2000

This paper introduces to design analog circuits with Verilog-A. It is a tool for design and simulation of analog ICs in behavioral level. Verilog-A has been already established standard and used to IP development in USA. We have proved the possibility of Verilog-A by comparing with measurement data of a fabricated 235MHz PLL circuit. This paper also describes another advantage of Verilog-A.

• 전자공학회논문지A
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• 제33A권6호
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• pp.220-229
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• 1996

We presetn sytem-level simulation methodology as well as environment setup established for CDMA digtial cellular mobile station in an effort to verify CDMA modem ASIC design. To make the system-level simulation feasible, behavioral modeling of a microcontroller was first carried out with VHDL. In addition, models written in C language were also developed to provide ASIC with realistic input data. Finally, the netlist of CDMA modem ASIC was loaded on the a hardware accelerator, which was interfaced with VHDL simulator, and ismulation was performed by excuting the actual CDMA call processing software. Simulation resutls thus obtained were confirmed by comparing them with the emulation resutls from the actual system constructed on hardware modeler. these methods were proved to be effective in both discovering in advance malfunctions when embedded in the system or design errors of ASIC and reducing simulation time by a factor of as much as 20 in case of simulation at gate-level.

• 한국컴퓨터산업학회논문지
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• 제9권4호
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• pp.157-170
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• 2008

본 연구에서는 메사츄세츄공과대학 마이크로전자 연구소에서 개발된 프로세서 PARWAN(PAR-1)으로 불리우는 줄여진 프로세서(a reduced processor)를 VHDL을 이용하여 Behavioral Leve에서 기술하고 Dataflow Level에서 상호 연결하여 기술하였고, VHDL로 설계된 CPU의 동작을 확인하고 시뮬레이션하기 위하여 Test-bench 방식을 이용하였다. <중략> 제시된 방식은 설계의 정보교환이 용이하고 동작의 표현이 정확하고 간결하였으며, 설계의 문서화가 용이하며, 구성된 프로세서의 동작을 확인하기가 용이하였다. VHDL의 Behavioral 기술은 설계자에게 설계된 시스템을 확인할 때 많은 도움을 주었으며 Dataflow 기술은 설계의 버스연결과 레지스터 구조를 확인할 때 유용하게 사용할 수 있었다.

• Nuclear Engineering and Technology
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• 제55권6호
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• pp.2246-2255
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• 2023

Evacuation time estimation (ETE) is crucial for the effective implementation of resident protection measures as well as planning, owing to its applicability to nuclear emergencies. However, as confirmed in the Fukushima case, the ETE performed by nuclear operators does not reflect behavioral features, exposing thus, gaps that are likely to appear in real-world situations. Existing research methods including surveys and interviews have limitations in extracting highly feasible behavioral features. To overcome these limitations, we propose a VR-based immersive experiment system. The VR system realistically simulates nuclear emergencies by structuring existing disasters and human decision processes in response to the disasters. Evacuation behavioral features were quantitatively extracted through the proposed experiment system, and this system was systematically verified by statistical analysis and a comparative study of experimental results based on previous research. In addition, as part of future work, an application method that can simulate multi-level evacuation dynamics was proposed. The proposed experiment system is significant in presenting an innovative methodology for quantitatively extracting human behavioral features that have not been comprehensively studied in evacuation. It is expected that more realistic evacuation behavioral features can be collected through additional experiments and studies of various evacuation factors in the future.

• 한국정보처리학회논문지
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• 제2권4호
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• pp.603-610
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• 1995

본 논문에서는 함수 기능에서 로직 게이트 기능까지 시뮬레이션 가능한 고성능의 로직 시뮬레이터(HSIM) 개발에 대해서 논한다. 개발된 로직 시뮬레이터는 입력부, 시 뮬레이터 본체, 출력부로 구성되어 있으며, 입력부에는 네트 리스트 컴파일러, 부품 정보 컴파일러가 포함된다. 시뮬레이터 본체에는 시뮬레이션 속도를 높이기 위한 각종 기술과 시뮬레이터의 중심 부분인 시뮬레이션 엔진 등이 소속되어 있다. 출력부에는 시뮬레이션 결과를 분석하는 파형 분석기가 있다. 개발된 시뮬레이터 본체의 주요 특 징은 점진적 로더를 사용하여 컴파일된 부품 기능들을 시뮬레이션 엔진에서 직접 로드 하여 시뮬레이션을 수행한다. 이렇게 한 결과 기존의 유릿 딜레어 event-driven interpretive 시뮬레이터와 비교했을 때 55% 이상 속도가 빠른 효과적인 성능 향상을 달성했다.