• Journal of Internet Computing and Services
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• v.3 no.3
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• pp.87-93
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• 2002

A complex network and a parallel computer are made up of interconnected switching units. The role of a switching unit is to set up a connection between an input port and an output port, according to the routing information. We proposed our switching network with a remodeled architecture is a newly modified Banyan network with eight input and output ports. We have analysed the maximum throughput of the revised switch. Our analyses have shown that under the uniform random traffic load, the FIFO discipline is limited to 70%, The switching system consists of an input control unit, a switch unit and an output control unit. Therefore the result of the analyses shows that the results of the networking simulation with the new switch are feasible and if we adopt the new architecture of the revised model of the Banyan switch, the hardware complexity can be reduced. The FIFO discipline has increased by about 11% when we compare the switching system with the input buffer system. We have designed and verified the switching system in VHDL using Max＋plusII. We also designed our test environment including micro computers, the base station, and the proposed architecture. We proposed a new architecture of the Banyan switch for BISDN networks and parallel computers.

• Journal of Korean Institute of Industrial Engineers
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• v.19 no.1
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• pp.47-59
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• 1993

Recently, Broadband ISDN(B-ISDN) has received increased attention as a communication architecture which can support multimedia applications. Also, Asynchronous Transfer Mode(ATM) is considered as a promising technique to transfer and switch various kinds of media, such as telephone speech, data and motion video. Comparisons among a variety of ATM switching systems which have already been proposed will provide quite useful information for the new ATM switching system design. To facilitate the comparison, we introduce the design requirements and classification criteria for the ATM switch, and propose a performance analysis model for the Banyan network which is the basic switching fabric of most multi-stage ATM switching systems. The model is based on the standard discrete-time Markov chain analysis and can be conveniently used for extensive Banyan network analysis. The computational results are also presented.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.1B
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• pp.1-7
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• 2010

In this paper, a high-performance fault-tolerant switching network using a deflection self-routing was proposed. From an abstract algebraic analysis of the topological properties of the Delta network, which is a baseline switching network, we derive the Multidimensional Ring-Delta network: a multipath switching network using a deflection self-routing algorithm. All of the links including already existing links of the Delta network are used to provide the alternate paths detouring faulty/congested links. We ran a simulation analysis under the traffic loads having the non-uniform address distributions that are usual in Internet. The throughput of $1024\;{\times}\;1024$ switching network proposed is better than that of the 2D ring-Banyan network by 13.3 %, when the input traffic load is 1.0 and the hot ratio is 0.9. The reliability of $64\;{\times}\;64$ switching network proposed is better than that of the 2D ring-Banyan network by 46.6%.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.9
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• pp.73-80
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• 2004

In this paper, we present the cell resequencing buffer to solve the cell sequence integrity problem of the Cyclic banyan network that is a high-performance fault-tolerant cell switch. By offering multiple paths between input ports and output ports, using the deflection self-routing, the Cyclic banyan switch offer high reliability, and it also solves congestion problem for the internal links of the switch. By the way, these multiple paths can be different lengths for each other. Therefore, the cells departing from an identical source port and arriving at an identical destination port can reach to the output port as the order that is different from the order arriving at input port. The proposed cell resequencing buffer is a hardware sliding window mechanism. to solve such cell sequence integrity problem. To calculate the size of sliding window that cause the prime cost of the presented device, we analyzed the distribution of the cell delay through the simulation analyses under traffic load that have a nonuniform address distribution that express tile Property of traffic of the Internet. Through these analyses, we found out that we can make a cell resequencing buffer by which the cell sequence integrity is to be secured, by using a, few of ordinary memory and control logic. The cell resequencing buffer presented in this paper can be used for other multiple paths switching networks.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.3 no.4
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• pp.274-279
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• 2002

ATM packet switching technologies for the purpose of the B-ISDN service are focused on high performance which represents good qualities on throughput, packet loss, and packet delay. ATM switch designs on a class of parallel interconnection network have been researched. But these are based on the self-routing function of it. It leads to conflict with each other, and to lose the packets. Therefore, this paper proposes the method based on Sort-Banyan network should be adopted for optimal routing algorithm. It is difficult to expect good hardware complexity. For good performance, a switch design based on the development of new routing algorithm is required. For the design of switch network, the packet distributor and multiplane are proposed. They prevent each packet from blocking as being transmitted selectively by two step distributed decision algorithm. This switch will be proved to be a good performance switch network that internal blocking caused from self-routing function is removed. Also, it is expected to minimize the packet loss and decrease the packet delay according to packet transmission.

• Journal of KIISE:Information Networking
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• v.31 no.3
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• pp.335-346
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• 2004

In this paper, we present a high-performance fault-tolerant switching networks using a deflection self-routing scheme, and present fault-diagnosis method for the network. We use the facts: 1) Each stage of the Banyan network is arrayed as the sequences of a Cyclic group of SEs. 2) There is the homomorphism between adjacent stages from a view of self-routing, so that all of each Cyclic group is the subgroup of the Cyclic group in the next stage, and there are factor groups due to such subgroup and homomorphism. We provide high-performance fault-tolerant switching networks of which the all links including augmented links are used as the alternate links detouring faulty links. We also present the fault diagnosis scheme for the proposed switching network that provide multiple paths for each input-output pair.

• The Transactions of the Korea Information Processing Society
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• v.7 no.4
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• pp.1073-1081
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• 2000

This paper proposes a new fault-tolerant technique for bitonic sorting networks which can be used for designing ATM switches based on Batcher-Banyan network. The main goal in this paper is to design a cost-effective fault-tolerant bitonic sorting network. In order to recover a fault, additional comparison elements and additional links are used. A Dynamic Redundant Bitonic Sorting (DRBS) network is based on the Dynamic Redundant network and can be constructed with several different variations. The proposed fault-tolerant sorting network offers high fault-tolerance; low time delays; maintenance of cell sequence; simple routing; and regularity and modularity.

• Journal of KIISE:Information Networking
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• v.28 no.3
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• pp.447-453
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• 2001

In this paper, we consider the scheduling of SE(switching element)-disjoint multicasting in photonic Banyan-type switching networks constructed with directional couplers. This ensures that at most, one connection holds each SE in a given time thus, neither crosstalk nor blocking will arise in the network. Such multicasting usually takes several routing rounds hence, it is desirable to keep the number of rounds(i.e., scheduling length) to a minimum. We first present the necessary and sufficient condition for connections to pass through a common SE(i.e., make crosstalk) in the photonic Banyan-type networks capable of supporting one-to-many connections. With definition of uniquely splitting a multicast connection into distinct subconnections, the crosstalk relationship of a set of connections is represented by a graph model. In order to analyze the worst case crosstalk we characterize the upper bound on the degree of the graph. The successor paper(Part II)[14] is devoted to the scheduling algorithm and the upper bound on the scheduling length. Comparison with related results is made in detail.

• The Transactions of the Korea Information Processing Society
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• v.6 no.5
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• pp.1212-1218
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• 1999

This paper proposes a new multipath interconnection network(MIN) structure for improving performance which uses widely in the design of multiprocessing, ATM system and VOD server. For improving performance such as passthrough ratio and packet latency, it proposes new routing method which routes one of the collided packets into the i+1-th switching stage of the adding Banyan MIN network when it occurred collision at the i-th switching stage of the basic MIN again when they collide each other. The new improved performance MIN network has been compared with MBSF, TBSF and PBSF structured MIN network from the viewpoint of passthrough ratio and the number of switching stage vs. passthrough ratio. It is shown to improve a performance and to be a simple structure which reducing the number of switching stage of adding MIN in comparison with other structured MIN including TBSF.

• Proceedings of the KAIS Fall Conference
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• 2002.11a
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• pp.209-211
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• 2002

본 연구에서는 비교적 하드웨어의 복잡성보다는 효율적인 Routing 알고리즘을 통하여 스위칭 네트워크의 성능을 향상시킬 수 있는 Sort-Banyan을 기본으로 한 스위칭 구조를 근간으로 하여 하드웨어 구조의 개선과 그에 맞는 최적의 Routing 알고리즘을 개발하고자 한다. 따라서 고속 통신망의 스위치 네트워크를 구현하기 위해 두 단계의 패킷 분배 결정 알고리즘을 구성하고 그에 따라 분배를 결정하여 패킷이 전송될 때 출력 단에서 충돌이 발생하지 않도록 사전에 선택적으로 전송함으로서 패킷의 손실을 방지하는 패킷 스위치 네트워크를 제안한다.