• Proceedings of the IEEK Conference
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• 2001.06a
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• pp.281-284
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• 2001

In this paper, we design the Sorting-Banyan network with an efficient buffer and sorting management schema that makes switch be capable of supporting delay sensitive as well as loss sensitive. The proposed switching network is remodeled that based on Batcher-banyan network that have eight input and output ports The structure of designed switching network is constructed of modified banyan network with 2-way routing paths and two plane sorting networks. we have analysed the maximum throughput of the switch, under the uniform random traffic load, the FIFO discipline has increased by about 11% when we compare the switching system with the input buffering system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.10B
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• pp.1841-1851
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• 1999

Banyan network has been widely employed as a basic building block for ATM switches. But the banyan network has very low routing capacity because of the internal blocking problem. Hence, a dilated banyan network has been used as one solution that can overcome the internal blocking problem. However, tremendous network capacity is wasted in the dilated network In this paper, we propose a dilated banyan network with deflection routing and recirculation mechanism to fully utilize the wasted capacity. The performance of the proposed switch is analysed under uniform traffic assumption. Numerical and simulation results show that the proposed switch yields a significant improvement of the maximum throughput as compared that of the pure dilated banyan network.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 1997.11a
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• pp.147-161
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• 1997

In the future, the performance of B-lSDN offering the multimedia and a various service depends on the performance of switch that is the important factor consisting of network. Bufferless banyan network consisted of MIN(multistage interconnection network) selected for- the fabric of ATM switch and has a limitation of performance because of blocking. Input buffered banyan networks with FIFO(first-in first-out) buffering scheme for the reduction of blocking and the cell bypass queueing theory for the reduction of HOL(head of line) blocking were seperately compared of the performance of switch. Specially input buffered banyan networks were applied monotonic buffering scheme that was proposed. As a result of simulation, Buffered Banyan Network with cell bypass queueing theory showed better performance than FIFO type input buffered Banyan network. Monotonic increase buffering scheme showed better performance than Monotonic decrease buffering scheme.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.43 no.5
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• pp.861-865
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• 1994

By using Neural Networks, a 8$\times$8 Banyan network controller is designed and implemented. In order to solve internal blocking and output blocking, Winner-Take-All method is used. The longer queue takes higher priority. First-in-first-out method is used among the non-blocking cells in the queue selected.The required time to select a cell is 2.7 $\mu$sec for 155Mbps. The implemented controller using Xilinx FPGA chip selects cells within 2.5$\mu$sec.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.7
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• pp.1756-1764
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• 1996

In this paper, we propose a new switch element of buffered Banyan network and analysis it. The proposed switch element consists of CASO(Content ASsociated Output) buffers, its controller and 2*2 crossbar switch. This switch element increase the performance of buffered Banyan network by removing HOL blocking. Also, we analyze the proposed switch element by mathematical modelling method based on MY analysis model which is one of earier proposed models.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.888-891
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• 2002

Banyan network is a popular and basic structure of the multistage ATM switches. This paper presents a novel approach to resolve the internal blocking of the banyan network by using Non-Blocking Permutation Generator (NBPG). The NBPG performs two functions, i.e., the first is to extract the conflict cells from the incoming cells and the second is to re-assign new input port addresses to the conflict cells. As a result, NBPG generates non-blocking I/O permutations. To estimate the performance of NBPG, we provide several simulation results.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.8
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• pp.21-31
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• 1998

In this paper, a new algorithm is proposed which distributes multicast cells in a copy network. The dual copy network is composed of running adder network, distributor, dummy address encoder, and broadcasting network. It is operated lower input address and higher one simultaneously by the distribution algorithm. As a result, for each input has a better equal opportunity of processing, cell delay and hardware complexity are reduced in copy network. Also, for it adopts the broadcasting network from an expansion Banyan network with binary tree and Banyan network, overflow probability is reduced to a half in that network. As a result of computer simulation, the copy network processed by the distribution algorithm is remarkably improved in cell delay of input buffer according to all input loads.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.122-125
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• 1999

In this paper, we propose a new architecture of the Banyan switch for a high speed networking and the high speed parallel computer. The proposed switching network with a remodeled architecture is a newly modified Banyan network with eight input and output pots, respectively. We have analysed the maximum throughput of the revised switch. Our analyses has shown that under the uniform random traffic load, the FIFO discipline is limited to 70％. Therefore the result of the analyses shows that the results of the networking simulation with the new switch are feasible and if we adopt such as new architecture of the revised model of the Banyan switch, the hardware complexity can be reduced. The FIFO discipline has increased about 11% when we compare the switching system with the input buffer system. We have designed and verified the new switching system in VHDL.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.537-540
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• 2000

In this paper, we propose and design new architecture of the modified Banyan switch for a high speed networking and the high speed parallel computer. The proposed switching network with a remodeled architecture is a newly modified Banyan network with eight input and output ports. The switch scheme is that two packets may arrive on different inputs destined for the same output. We have analyzed the maximum throughput of the revised switch. The result of the analyses shows good agreement simulation and if we adopt such architecture of the revised model of the Banyan switch, the hardware complexity can be reduced. The FIFO discipline has increased about lloio when we compare the switching system with the input buffer system. We have designed and verified the switching system in VHDL.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.4B
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• pp.282-287
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• 2003

A network is made up of interconnected switching units. The role of a switching unit is to set up a connection between and input port and an output, according to the routing information. But then the most switching network use Banyan switch, their occurs the internal blocking , which attempts to use the same link two cells. This paper proposed and designed for a improvement Batch-Banyan network which can routed two path assignment between its input ports and output ports without only blocking. The network is constructed of two sorting blocks ($4{\times}4$), one switch network($8{\times}8$) block. As a result, the switch network performance increased 4% reduced to half of the hardware complexity of sorting boxes when compare the new switching system with Batcher-Banyan network system.