• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.175.1-175.1
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• 2014

Despite growing interest in Ge as a possible alternative to Si, reliable data on Ge surface has been relatively scarce. Using low temperature scanning tunneling microscopy (STM), we investigate band-bending effects of localized charge traps at Ge(001) surface at 78 K. For this investigation, we prepared nearly defect-free Ge(001) surface by keeping the background pressure to < $1{\times}10^{-10}$ mbar during outgassing. Ge(001) surfaces this obtained exhibit a flat-band condition, and deposition of charge traps induce a distinct, sharp boundary between pinned and depinned surface area in the constant current mode STM images. We will show the tip-surface interaction plays an essential role in producing the boundary, and discuss about the conditions that enable the pinning effect.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.679-682
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• 2005

Negative-differential conductance (NDC) characteristics as well as negative-differential trans-conductance (NDT) characteristics have been observed in the room temperature I-V characteristics of Field-induced Inter-band Tunneling Effect Transistors (FITETs). These characteristics have been explained with inter-band tunneling physics, from which, inter-band tunneling current flows when the energy bands of degenerately doped regions align, and it does not flow when they don't. FITET is an SOI device and the body region is not directly connected to the external terminal. Therefore, Fermi energy in the body region is determined by electrical coupling among four regions - gate, source, drain and substrate. So, a quasi Fermi energy of the majority carriers in the floating body region can be changed by external voltages, and this causes the energy band movements in the body region, which determine whether the energy bands between degenerately doped junctions aligns or not. This is a key point for an explanation of NDT and NDC characteristics. In this paper, a quasi Fermi energy movement in the floating body region of FITET was investigated by a device simulation. This result was applied for the description of relation between quasi Fermi energy in the body region and external gate bias voltage.

• Journal of Electrical Engineering and Technology
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• v.8 no.6
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• pp.1481-1486
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• 2013

In this paper, a new two dimensional (2D) analytical model of a Dual Material Gate tunnel field effect transistor (DMG TFET) is presented. The parabolic approximation technique is used to solve the 2-D Poisson equation with suitable boundary conditions. The simple and accurate analytical expressions for surface potential and electric field are derived. The electric field distribution can be used to calculate the tunneling generation rate and numerically extract tunneling current. The results show a significant improvement of on-current and reduction in short channel effects. Effectiveness of the proposed method has been confirmed by comparing the analytical results with the TCAD simulation results.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.630-634
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• 2016

We report the computer aided design results for a GaSb/InAs broken-gap gate all around nanowire tunneling FET (TFET). In designing, the semi-empirical tight-binding (TB) method using $sp3d5s^*$ is used as band structure model to produce the bulk properties. The calculated band structure is cooperated with open boundary conditions (OBCs) and a three-dimensional $Schr{\ddot{o}}dinger$-Poisson solver to execute quantum transport simulators. We find an device configuration for the operation voltage of 0.3 V which exhibit desired low sub-threshold swing (< 60 mV/dec) by adopting receded gate configuration while maintaining the high current characteristic ($I_{ON}$ > $100 {\mu}A/{\mu}m$) that broken-gap TFETs normally have.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.1
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• pp.40-49
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• 2001

We have developed a repeatable process of forming uniform, small-size and high-density self-assembled Si nano-crystals. The Si nano-crystals were fabricated in a conventional LPCVD (low pressure chemical vapor deposition) reactor at $620^{\circ}c$ for 15 sec. The nano-crystals were spherical shaped with about 4.5 nm in diameter and density of $5{\times}l0^{11}/$\textrm{cm}^2$. More uniform dots were fabricated on nitride film than on oxide film. To take advantage of the above-mentioned characteristics of nitride film while keeping the high interface quality between the tunneling dielectrics and the Si substrate, nitride-oxide tunneling dielectrics is proposed in n-channel device. For the first time, the single electron effect at room temperature, which shows a saturation of threshold voltage in a range of gate voltages with a periodicity of ${\Delta}Ｖ_{GS}\;{\approx}\;1.7{\;}V$, corresponding to single and multiple electron storage is reported. The feasibility of p-channel nano-crystal memory with thin oxide in direct tunneling regime is demonstrated. The programming mechanisms of p-channel nano-crystal memory were investigated by charge separation technique. For small gate programming voltage, hole tunneling component from inversion layer is dominant. However, valence band electron tunneling component from the valence band in the nano-crystal becomes dominant for large gate voltage. Finally, the comparison of retention between programmed holes and electrons shows that holes have longer retention time.

• Journal of information and communication convergence engineering
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• v.16 no.4
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• pp.248-251
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• 2018

To research the characteristics of $TiO_2$ as an insulator, $TiO_2$ films were prepared with various annealing temperatures. It was researched the currents of $TiO_2$ films with Schottky barriers in accordance with the contact's properties. The potential barrier depends on the Schottky barrier and the current decreases with increasing the potential barrier of $TiO_2$ thin film. The current of $TiO_2$ film annealed at $110^{\circ}C$ was the lowest and the carrier density was decreased and the resistivity was increased with increasing the hall mobility. The Schottky contact is an important factor to become semiconductor device, the potential barrier is proportional to the hall mobility, and the hall mobility increased with increasing the potential barrier and became more insulator properties. The reason of having the high mobility in the thin films in spite of the lowest carrier concentration is that the conduction mechanism in the thin films is due to the band-to-band tunneling phenomenon of electrons.

• Journal of Korea Society of Industrial Information Systems
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• v.16 no.5
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• pp.1-8
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• 2011

This paper proposes a new input pattern generator for minimal leakage power in the nanometer CMOS technology considering all the leakage current components (sub-threshold leakage, gate tunneling leakage, band-to-band tunneling leakage). Using the accurate macro-model, a heuristic algorithm is developed to generate a input pattern for the minimum leakage. The algorithm applies to ISCAS85 benchmark circuits, and the results are compared with the results of Hspice. The simulation result shows that our method's accuracy is within a 5% difference of the Hspice simulation results. In addition, the simulation time of our method is far faster than that of the Hspice simulation.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.3
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• pp.46-52
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• 1994

We investigated theoretically the current-voltage characteristics of resonant tunneling diodes with a single quantum well structure. using a self-consistent method. This method is a numerical analysis which is able to include the effects of the undoped spacer layer and the band bending by charge accumulation and depletion on the contact layers which have not been considered in the flat-band model reported by Esaki. so that it is better suited to explain experimental results. The structure used is an $AL_{0.5}Ga_{0.5}AS/GaAs/Al_{0.5}Ga_{0.5}AS$ single quantum well. In this work. we estimate the theoretical current-voltage characteristics of the same structure, and then, the dependence of the current-voltage curves on the thickness of undoped spacer layers sandwiched between the barrier and highly n-doped GaAs contact layer.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.7
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• pp.45-55
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• 1997

Electircal characteristics of HgCdTe photodiodes with a heterostructure to achieve high performance are analyzed numerically. A two-dimensional device simulator which can handle a HgCdTe heterostructure, was developed for this work. The effects of band nonparabolicity, carrier degeneracy, and band-offset of heterointerace are included in a carrier transport model. A unified generation-recombination model includes simultaneously phonon-assisted tunneling and pure tunneling of carriers via traps is newly employed for describing the electric field and temperature dependency of dark current effectively. Furthermore, to accurately predict the effect mole fraction variations on genration rates, ray-trace algorithm is incorporated in the our simulator. Under the various circumstances such as dark, illumination, and surface states, electrical properties of planar heterostructure photodiode are presented and those of homojunction are compared. These results serve as a explanation of cap layer's role on performance.

• Proceeding of EDISON Challenge
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• 2016.03a
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• pp.368-372
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• 2016

In this paper, the physics-based analytical model of transition metal dichalcogenide (TMD)-based double-gate (DG) tunneling field-effect transistors (TFETs) is proposed. The proposed model is derived by using the two-dimensional (2-D) Landauer formula and the Wentzel-Kramers-Brillouin (WKB) approximation. For improving the accuracy, nonlinear and continuous lateral energy band profile is applied to the model. 2-D density of states (DOS) and two-band effective Hamiltonian for TMD materials are also used in order to consider the 2-D nature of TMD-based TFETs. The model is validated by using the tight-binding non-equilibrium Green's function (NEGF)-based quantum transport simulation in the case of monolayer molybdenum disulfide ($MoS_2$)-based TFETs.