• 대한수학회보
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• 제46권4호
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• pp.721-741
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• 2009

Consider RSA with N = pq, q < p < 2q, public encryption exponent e and private decryption exponent d. We first study cryptanalysis of RSA when certain amount of the Most Significant Bits (MSBs) or Least Significant Bits (LSBs) of d is known. The basic lattice based technique is similar to that of Ernst et al. in Eurocrypt 2005. However, our idea of guessing a few MSBs of the secret prime p substantially reduces the requirement of MSBs or LSBs of d for the key exposure attack. Further, we consider the RSA variant proposed by Sun and Yang in PKC 2005 and show that the partial key exposure attack works significantly on this variant.

• 대한전기학회논문지:시스템및제어부문D
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• 제55권5호
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• pp.229-235
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• 2006

High speed PC-based DIO(Digital I/O) system that consists of a master device and slave I/O devices is developed. The PCI interfaced master device controls all of serial communications, reducing the load on the CPU to a minimum. The slave device is connected from the master device and another slave device is connected to the slave device, it can repeated to maximum 64 slave devices. The slave device has 3 types I/O mode, such as 16 bits input-only, 16 bits output-only, and 8bits input-output. The master device has 2 rings which can take 64 slaves each. Therefore, total I/O points covered by the master is 2048 points. The slave features 3 types of input/output function interchangeability by DIP switch settings. Library, application, and device driver software for the DIO system that have a secure and a convenient functionality are developed.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 제36회 하계학술대회 논문집 D
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• pp.2806-2808
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• 2005

The Controller Area Network (CAN) is being widely used for real-time control application and small-scale distributed computer controller systems. When the stuff bits are generated by bit-stuffing mechanism in the CAN network, it causes jitter including variations in response time and delay. In order to eliminate this jitter, stuff bit must be controlled to minimize the response time and reduce the variation of data transmission time. At first, this paper shows that conventional CAN protocol causes the transmission time delay. Secondly, this paper proposes the method to reduce the stuff bits by restriction of available identifier. Finally, data manipulation method can be reduced the number of stuff-bits in the data field. The proposed restriction method of ID and manipulating data field are pretty useful to the real-time control strategy with respect to performance. These procedures are implemented in local controllers of the ISHURO (Inha Semyung Humanoid Robot).

• ETRI Journal
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• 제27권2호
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• pp.223-226
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• 2005

This paper presents the application of a turbo coding technique combined with a bandwidth efficient method known as trellis-coded modulation. A transformation applied to the incoming I-channel and Q-channel symbols allows the use of an off-the-shelf binary/quadrature phase shift keying (B/QPSK) turbo decoder without any modifications. A conventional turbo decoder then operates on transformed symbols to estimate the coded bits. The uncoded bits are decoded based on the estimated coded bits and locations of the received symbols.

• 대한전자공학회논문지
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• 제27권8호
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• pp.1255-1259
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• 1990

A new ripple analog-to-digital converter (ADC) has been developed. It consists of two parallel ADCs and a switching network. The circuit operates on the analog input signal in two serial steps. First, a coarse conversion is made to determine the most significant bits by the first parallel ADC. The resultant bits control the switching network to connect a series resistor segment, within which the analog signal is contained, to the second parallel ADC. At second step, a fine conversion is made to determine the least significant bits by the second parallel ADC. The circuit requires 2(2\ulcorner\ulcorner1) comparators, 2(2\ulcorner\ulcorner resistors, and 2(2\ulcorner\ulcorner swithches for N-bit resolution.

• Bulletin of the Korean Chemical Society
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• 제32권8호
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• pp.2657-2660
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• 2011

1,2,4-Triazoles and quinoxalines were found to display various pharmacological activities. Hence a series of 1-aryl-4-methyl-1,2,4-triazolo[4,3-a]quinoxalines were synthesized. Due to various advantages of organic reactions under solvent-free conditions these compounds were developed using iodobenzene diacetate under solvent-free conditions. The synthesized compounds were characterized by elemental microanalysis, infrared spectroscopy, $^1H$ NMR, $^{13}C$ NMR and HRMS. All the synthesized compounds were investigated for their antitubercular activity and 5g was found to the most active compound.

• 한국통신학회논문지
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• 제21권4호
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• pp.834-847
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• 1996

A selective coding scheme is proposed that describes a method for coding image sequences distinguishing bits between background and target region. The suggested method initially estimates global motion parameters and local motion vectors. Then segmentation is performed with a hierarchical clustering scheme and a quadtree algorithm in order to divide the processing image into the backgraound and target region. Finally image coding is done by assigning more bits to the target region and less bits to background so that the target region may be reconstructed with high quality. Simulations show that the suggested algorithm performs well especially in the circumstances where background changes and target regionis small enough compared with that of background.

• Journal of information and communication convergence engineering
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• 제7권4호
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• pp.516-520
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• 2009

RSA crypto-processors equipped with more than 1024 bits of key space handle the entire key stream in units of blocks. The RSA processor which will be the target design in this paper defines the length of the basic word as 128 bits, and uses an 256-bits register as the accumulator. For efficient execution of 128-bit multiplication, 32b*32b multiplier was designed and adopted and the results are stored in 8 separate 128-bit registers according to the status flag. In this paper, an efficient method to execute 128-bit MAC (multiplication and accumulation) operation is proposed. The suggested method pre-analyzed the all possible cases so that the MAC unit can remove unnecessary calculations to speed up the execution. The proposed architecture prototype of the MAC unit was automatically synthesized, and successfully operated at 20MHz, which will be the operation frequency in the RSA processor.

• Journal of information and communication convergence engineering
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• 제5권4호
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• pp.311-315
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• 2007

This paper proposes a revised query tree algorithm in RFID systems. The proposed QT_ecfi algorithm revises the QT algorithm, which has a memory-less property. In the QT_ecfi algorithm, the tag will send the remaining bits of their identification codes when the query string matches the first bits of their identification codes. When the reader receives all the responses of the tags, it knows which bit is collided. If the collision occurs in the last bit, the reader can identify two tags simultaneously without further query. While the tags are sending their identification codes, if the reader detects a collision bit, it will send a signal to the tags to stop sending. According to the simulation results, the QT_ecfi algorithm outperforms the QT algorithm in terms of the number of queries and the number of response bits.

• 전자공학회논문지C
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• 제34C권3호
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• pp.23-36
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• 1997

In tis paper, sthe new data model for the hardware implementation of lempel-ziv compression algorithm was proposed. Traditional model generates the codeword which consists of 3 bytes, the last symbol, the position and the matched length. MSB (most significant bit) of the last symbol is the comparession flag and the remaining seven bits represent the character. We confined the value of the matched length to 128 instead of 256, which can be coded with seven bits only. In the proposed model, the codeword consists of 2 bytes, the merged symbol and the position. MSB of the merged symbol is the comression flag. The remaining seven bits represent the character or the matched length according to the value of the compression flag. The proposed model reduces the compression ratio by 5% compared with the traditional model. The proposed model can be adopted to the existing hardware architectures. The incremental factors of the compression ratio are also analyzed in this paper.