• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.8C
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• pp.822-829
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• 2009

This paper proposes a new method of improving the quality of High Efficiency Advanced Audio Coding (HE-AAC). HE-AAC encodes input source by allocating bits for each scalefactor bands appropriately according to human ear's psychoacoustic property. As a result, insufficient bits are assigned to the bands which have relatively low energy. This imbalance between different energy bands can cause decreasing of sound quality like musical noise. In the proposed system, a Linear Prediction (LP) module is combined with HE-AAC as a pre-processor to improve sound quality by even bits distribution. To apply accurate human being's psychoacoustic property, the psychoacoustic model uses Fast Fourier Transform (FFT) spectrum of original input signal to make masking threshold. In its implementation, masking threshold of psychoacoustic model is normalized using the LP spectral envelope in prior to quantization of the LP residual. Experimental result shows that, the proposed algorithm allocates bits appropriately for insufficient bits condition and improves the performance of HE-AAC.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.7A
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• pp.994-1004
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• 2000

In this paper, bitstreams are composed of using H.263 for a moving picture coding in the band-limited and error-prone environment such as wireless environment. EREC sub-frames are implemented by applying the proposed EREC algorithm in order to be UEP for the real data parts of implemented bitstreams. Because those are able to do resynchronization with a block unit, propagation of the error can be minimized, and the position of the important bits such as INTRADC and MVD can be known. Class is separated using the position of these important bits, and variable puncturing tables are designed by the class informations and the code rates of turbo codes are differently designed in according to the class. Channel coding used the turbo codes, and an interleaver to be designed in the turbo codes does not eliminate redundancy bits of the important bits in applying variable code rates of EREC sub-frames unit and is always the same at the transmitter and the receiver although being variable frame size. As a result of simulation, UEP with the code rate similar to EEP is obtained a improved result in the side of bit error probability. And the result of applying it to image knows that the subjective and objective quality have been improved by the protection of important bits.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.6A
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• pp.537-543
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• 2007

In this paper, we propose a new stopping criterion for the turbo processing (Turbo-BLAST) of MIMO-OFDM system. To reduce the high computational complexity of turbo-BLAST, it is desirable to lessen the outer-loop iteration number. In a system such as IEEE 802.16e Mobile WiMax, no CRC bits are available except the last encoding packet of a transmitted burst, so early stopping criteria without the help of CRC bits are needed. The proposed criterion counts the sign differences between received parity bits and the re-encoded parity bits from received information bits. With the tail-biting code which is accepted for IEEE 802.16e, a method that the re-encoder operates at half complexity is also proposed. Computer simulations show that the proposed stopping criterion approaches the performance of GENIE aided criterion with less average number of iterations than the other early stopping criteria.

• Journal of Electrical Engineering and Technology
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• v.10 no.1
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• pp.436-442
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• 2015

In this paper, we develop an indoor localization device which embeds localization information into indoor light-emitting-diodes (LED) lighting systems. The key idea of our device is the use of the newly proposed "bit stuffing method". Through the use of stuff bits, our device is able to measure signal strengths even in transient states, which prohibits interference between lighting signals. The stuff bits also scatter the parts of the signal where the LED is turned on, thus provides quality indoor lighting. Additionally, for the indoor localization system based on RSSI and TDM to be practical, we propose methods for the control of LED lamps and compensation of received signals. The effectiveness of the proposed scheme is validated through experiments with a low-cost implementation including an indoor navigation task.

• ETRI Journal
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• v.23 no.1
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• pp.16-22
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• 2001

Efficient quantization methods of the line spectrum pairs (LSP) which have good performances, low complexity and memory are proposed. The adaptive quantization range method utilizing the ordering property of LSP parameters is used in a scalar quantizer and a vector-scalar hybrid quantizer. As the maximum quantization range of each LSP parameter is varied adaptively on the quantized value of the previous order's LSP parameter, efficient quantization methods can be obtained. The proposed scalar quantization algorithm needs 31 bits/frame, which is 3 bits less per frame than in the conventional scalar quantization method with interframe prediction to maintain the transparent quality of speech. The improved vector-scalar quantizer achieves an average spectral distortion of 1 dB using 26 bits/frame. The performances of proposed quantization methods are also evaluated in the transmission errors.

• ETRI Journal
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• v.30 no.1
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• pp.167-169
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• 2008

In this paper, we propose hardware architecture for a high-speed context-adaptive variable length coding (CAVLC) decoder in H.264. In the CAVLC decoder, the codeword length of the current decoding block is used to determine the next input bitstreams (valid bits). Since the computation of valid bits increases the total processing time of CAVLC, we propose two techniques to reduce processing time: one is to reduce the number of decoding steps by introducing a lookup table, and the other is to reduce cycles for calculating the valid bits. The proposed CAVLC decoder can decode $1920{\times}1088$ 30 fps video in real time at a 30.8 MHz clock.

• The Transactions of the Korea Information Processing Society
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• v.7 no.7
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• pp.2254-2263
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• 2000

This paper proposes an efficient predictive image-compression technique based on vector quantization of blocks of pels. In the proposed method edge contents of blocks control the selection of predictors and block shapes as well. The maximum number of bits assigned to quantizers has been in creased to 3bits/pel from 1/5bits/pel, the setting employed by forerunners in predictive vector quantization of images. This increase prevents the saturation in SNR observed in their results in high bit rates. The variable block shape is instrumental in eh reconstruction of edges. The adaptive procedure is controlled by means of he standard deviation ofp rediction errors generated by a default predictor; the standard deviation address a decision table which can be set up beforehand. eh proposed method is characterized by overall improvements in image quality over A-VQ-PE and A-DCT VQ, both of which are known for their efficient use of vector quantizers.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.6
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• pp.1241-1245
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• 2009

As FFT(Fast Fourier Transform) processor is used in OFDM(Orthogonal Frequency Division Multiplesing) system. According to increase requirement about mobility and broadband, Research about low power and low area FFT processor is needed. So research concern in reduction of memory size and complex multiplier is in progress. Increasing points of FFT increase memory area of FFT processor. Specially, SRU(Signal Reordering Unit) has the most memory in FFT processor. In this paper, we propose a reduced method of memory size of SRU in FFT processor. SRU of 64, 1024 point FFT processor performed implementation by VerilogHDL coding and it verified by simulation. We select the APEX20KE family EP20k1000EPC672-3 device of Altera Corps. SRU implementation is performed by synthesis of Quartus Tool. The bits of data size decide by 24bits that is 12bits from real, imaginary number respectively. It is shown that, the proposed SRU of 64point and 1024point achieve more than 28%, 24% area reduction respectively.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.3
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• pp.627-631
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• 2009

This paper presents a novel current steering cell matrix DAC(digital-to-analog converter) architecture to reduce decoder area. The current cell matrix of a existing architecture is selected by columns and lows thermometer code decoder of input bits. But The current cell matrix of a proposal architecture is divided 2n by the thermometer code decoder of upper input bits and are selected by the thermometer code decoder of middle and lower input bits. Because of this configuration, decoder numbers have increased. But the gate number that composed of decoder has decreased. In case of the designed 8 bit current steering cell matrix DAC, the gate number of decoder has decreased by about 55% in comparison with a existing architecture.

• Journal of Biomedical Engineering Research
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• v.7 no.1
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• pp.53-58
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• 1986

This paper represent the design of a digital modem which transmits the ECG data from an ambulatory arrhythmia monitor over the telephone lines to a large hospital for the instantaneous interpretations. The digital modem provides on-line communications between the patient and the central computer located near cardiologists. For commercial telephone lines, the transmitting error rates of the digital modem were measured 200 times at a speed of 300 baud. In those measurements, the block errors-results, due to the misinterpretation of start and stop bits, did not occur, The data bit errors which were due to a single bit interpreted incorrectly were 0.78 (bits/10 ) . Since the acceptable data bit error limit is 10 per 106 bits transmitted, the digital modem designed in this paper can be used for the clinical applications without any difficulty.