• Journal of Korea Multimedia Society
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• v.10 no.2
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• pp.269-277
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• 2007

Network clustering has been proposed to provide that sensor nodes minimize energy and maximize a network lifetime by configuring clusters, Although dynamic clustering brings extra overhead like as head changing, head advertisement, it may diminish the gain in energy consumption to report attribute tasks by using cluster heads. Therefore, this paper proposes a new routing algorithm which configures cluster to reduce the number of messages when establishing paths and reports to the sink by way of cluster heads when responding sens ing tasks. All sensor nodes only broadcast bitmap once and maintain a bitmap table expressed by bits, allowing them to reduce node energy and to prolong the network lifetime. After broadcasting, each node only updates the bitmap without propagation when the adjacent nodes broad cast same query messages, This mechanism makes nodes to have abundant paths. By modifying the query which requests sensing tasks, the size of cluster is designed dynamically, We try to divide cluster by considering the number of nodes. Then, all nodes in a certain cluster must report to the sub- sink node, The proposed routing protocol finds easily an appropriate path to report tasks and reduces the number of required messages for the routing establishment, which sensor nodes minimize energy and maximize a network lifetime.

• Journal of the Institute of Convergence Signal Processing
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• v.18 no.1
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• pp.13-20
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• 2017

In this paper, we evaluate the basic test results of the 32 Gbps observational equipment introduced as the back-end system for the wideband VLBI (Very Long Baseline Interferometry) observation of KVN (Korean VLBI Network). Radio astronomers want to make a large radio telescope that has excellent performance in order to observe the superfine structure of a celestial body, but a lot of money is needed. Therefore, in order to increase the sensitivity, the performance improvement of the receiving system and the method of observing the wide frequency bandwidth are introduced. To do this, we adopted a wideband sampling method for converting analog signals to digital with ultra-fast speeds and a wideband sampler for performing digital filtering in order to observe a wide observational frequency bandwidth. The wideband sampler (OCTAD-K) supports up to 16 Gsps-2bits sampling and supports a variety of observational bandwidth using digital filtering techniques. In particular, it is designed to support KVN's 4-frequency simultaneous observation system and VERA(VLBI Exploration of Radio Astrometry)'s 2-beam observation system. It can also support polKVN(Korean VLBI Network), KaVA(KVN and VERA Array), 32Gbps Direct Sampler, Digital Filter, Widebandarization observations and supports the standard VDIF(VLBI Data Interchange Format) format of observed data. In this paper, the performance of the system and the problem solving are described in detail after performing the factory inspection and field test before the system is introduced.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.7
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• pp.107-118
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• 2015

Although most current video coding standards set a fixed motion vector resolution like quarter-pel accuracy, a scheme supporting multiple motion vector resolutions can improve the coding efficiency of video since it can allow to use just required motion vector accuracy depending on the video content and at the same time to generate more accurate motion predictor. However, the selected motion vector resolution for each motion vector is a signaling overhead. This paper proposes a contradiction testing-based signaling scheme of the motion vector resolution. The proposed method selects a best resolution for each motion vector among multiple candidates in such a way to produce the minimum amount of coded bits for the motion vector. The signaling overhead is reduced by contradiction testing that operates under a predefined criterion at both encoder and decoder with a purpose of pruning irrelevant candidate motion vector resolutions from signaling responsibility. Experimental results verified that the proposed scheme is effective in reducing coded motion information by achieving its $Bj{\o}ntegaard$ delta bit rate (BDBR) gain of about 4.01% on average (and up to 15.17%) compared to the conventional scheme with a fixed motion vector resolution.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.7
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• pp.1227-1234
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• 2008

In this paper is designed a 256-bit synchronous OTP(one-time programmable) memory required in application fields such as automobile appliance power ICs, display ICs, and CMOS image sensors. A 256-bit synchronous memory cell consists of NMOS capacitor as antifuse and access transistor without a high-voltage blocking transistor. A gate bias voltage circuit for the additional blocking transistor is removed since logic supply voltage VDD(=1.5V) and external program voltage VPPE(=5.5V) are used instead of conventional three supply voltages. And loading current of cell to be programmed increases according to RON(on resistance) of the antifuse and process variation in case of the voltage driving without current constraint in programming. Therefore, there is a problem that program voltage can be increased relatively due to resistive voltage drop on supply voltage VPP. And so loading current can be made to flow constantly by using the current driving method instead of the voltage driving counterpart in programming. Therefore, program voltage VPP can be lowered from 5.9V to 5.5V when measurement is done on the manufactured wafer. And the sens amplifier circuit is simplified by using the sens amplifier of clocked inverter type instead of the conventional current sent amplifier. The synchronous OTP of 256 bits is designed with Magnachip $0.13{\mu}m$ CMOS process. The layout area if $298.4{\times}314{\mu}m2$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.253-256
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• 2009

This paper describes a core generator (FFT_Core_Gen) which generates Verilog HDL models of 8 different FFT/IFFT cores with $N=64{\times}2^k$($0{\leq}k{\leq}7$ for OFDM-based communication systems. The generated FFT/IFFT cores are based on in-place single memory architecture, and use a hybrid structure of radix-4 and radix-2 DIF algorithm to accommodate various FFT lengths. To achieve both memory reduction and the improved SQNR, a conditional scaling technique is adopted, which conditionally scales the intermediate results of each computational stage, and the internal data and twiddle factor has 14 bits. The generated FFT/IFFT cores have the SQNR of 58-dB for N=8,192 and 63-dB for N=64. The cores synthesized with a $0.35-{\mu}m$ CMOS standard cell library can operate with 75-MHz@3.3-V, and a 8,192-point FFT can be computed in $762.7-{\mu}s$, thus the cores satisfy the specifications of wireless LAN, DMB, and DVB systems.

• Journal of the Korea Society of Computer and Information
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• v.18 no.12
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• pp.1-9
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• 2013

Even though the multiple pages TLB are effective in improving the performance, a conventional method with OS support cannot utilize multiple page sizes in user application. Thus, we propose a new multiple-TLB structure supporting multiple page sizes for high performance and low power consumption without any operating system support. The proposed TLB is organised as two parts of a S-TLB(Small TLB) with a small page size and a L-TLB(Large TLB) with a large page size. Both are designed as fully associative bank structures. The S-TLB stores small pages are evicted from the L-TLB, and the L-TLB stores large pages including a small page generated by the CPU. Each one bank module of S-TLB and L-TLB can be selectively accessed base on particular one and two bits of the virtual address generated from CPU, respectively. Energy savings are achieved by reducing the number of entries accessed at a time. Also, this paper proposed the simple 1-bit LRU policy to improve the performance. The proposed LRU policy can present recently referenced block by using an additional one bit of each entry on TLBs. This method can simply select a least recently used page from the L-TLB. According to the simulation results, the proposed TLB can reduce Energy * Delay by about 76%, 57%, and 6% compared with a fully associative TLB, a ARM TLB, and a Dual TLB, respectively.

• Journal of Korean Tunnelling and Underground Space Association
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• v.21 no.4
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• pp.545-560
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• 2019

During EPB TBM tunnelling, an appropriate application of additives such as foam and polymer is an essential factor to secure the stability of TBM as well as tunnelling performance. From the '90s, there have been many studies on the optimal injection of additives worldwidely contrary to the domestic situation. Therefore, in this paper, the foam, which is widely adopted for soil conditioning, was selected as an additive in order to investigate the effect of foam injection on TBM performance through a series of laboratory excavation tests. The excavation experiments were carried out on artificial sandy soil specimens with consideration of the variance of FIR (Foam Injection Ratio), FER (Foam Expansion Ratio) and $C_f$ (Surfactant Concentration), which indicate the amount and quality of the foam. During the tests, torque values were measured, and the workability of conditioned soil was evaluated by comparing the slump values of muck after each experiment. In addition, a weight loss of the replaceable aluminum cutter bits installed on the blade was measured to estimate the degree of abrasion. Finally, the foam injection ratio for the optimal TBM excavation for the typical soil specimen was determined by comparing the measured torque, slump value and abrasion. Note that the foam injection conditions satisfying the appropriate level of machine load, mechanical wear and workability are essential in the EPB TBM operational design.

• Journal of Broadcast Engineering
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• v.24 no.2
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• pp.306-314
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• 2019

Since the resolutions of videos increase rapidly, there are continuing needs for effective video compression methods despite an increase in the transmission bandwidth. In order to satisfy such a demand, a reconstructive video coding (RVC) method by using a super resolution has been proposed. Since RVC reduces the resolution of the input video, when frames are compressed to the same size, the number of bits per pixel increases, thereby reducing coding artifacts caused by video coding. However, RVC method using super resolution is not effective in all target bitrates. Comparing the size of the loss generated while downsizing the resolution and the size of the loss caused by the video compression, only when the size of loss generated in the video compression is larger, RVC method can perform the improved compression performance compared to direct video coding. In particular, since HEVC has considerably higher compression performance than the previous standard video codec, it can be experimentally confirmed that the compression distortions become larger than the distortions of downsizing the resolution only in the very low-bitrate conditions. In this paper, we applied RVC based HEVC in various video types and measured the target bitrates that RVC method can be effectively applied.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.6
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• pp.17-28
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• 2002

XTR is a new method to represent elements of a subgroup of a multiplicative group of a finite field GF( $p^{6m}$) and it can be generalized to the field GF( $p^{6m}$)$^{[6,9]}$ This paper progress optimal extention fields for XTR among Galois fields GF ( $p^{6m}$) which can be aplied to XTR. In order to select such fields, we introduce a new notion of Generalized Opitimal Extention Fields(GOEFs) and suggest a condition of prime p, a defining polynomial of GF( $p^{2m}$) and a fast method of multiplication in GF( $p^{2m}$) to achieve fast finite field arithmetic in GF( $p^{2m}$). From our implementation results, GF( $p^{36}$ )longrightarrowGF( $p^{12}$ ) is the most efficient extension fields for XTR and computing Tr( $g^{n}$ ) given Tr(g) in GF( $p^{12}$ ) is on average more than twice faster than that of the XTR system on Pentium III/700MHz which has 32-bit architecture.$^{［6,10］/ ［6,10］/6,10］}$

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.6
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• pp.59-69
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• 2002

Many Linear attacks have introduced after M. Matsui suggested Linear Cryptanalysis in 1993. The one of them is the method suggested by B. Kaliski and M. Robshaw. It was a new method using multiple linear approximations to attack for block ciphers. It requires less known plaintexts than that of Linear Cryptanalysis(LC) by Matsui, but it has a problem. In this paper, we will introduce the new method using multiple linear approximation that can solve the problem. Using the new method, the requirements of the known plaintexts is 5(1.25) times as small as the requirements in LC on 8(16) round DES with a success rate of 95%(86%) respectively. We can also adopt A Chosen Plaintext Linear Attack suggested by L. R. Knudsen and J. E. Mathiassen and then our attack requires about $2^{40.6}$ chosen plaintexts to recover 15 key bits with 86% success rate. We believe that the results in this paper contain the fastest attack on the DES full round reported so far in the open literature.