• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.6A
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• pp.533-539
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• 2002

It is well known the fact that turbo lodes has better performance as the number of iteration and the interleaver size increases in the AWGN channel environment. However, as the number of iteration and the interleaver size are increased, it is required much delay and computation for iterative decoding, and caused the flattening effect phenomenon which is very litter BER performance improvement at the arbitrary SNR. In this paper, We proposed the new asymmetric turbo codes, which consist of parallel concatenated turbo codes that use mixed types of component codes with different not only constraint length but also generate polynomial and analyzed its BER performance for log-MAP decoding algorithm with frame size of 128, 256, 512 and 1024 bits, and coding rate of 1/3. As a results of simulation, proposed asymmetric turbo codes verify that its BER performance is superior to conventional symmetric turbo codes. It can be also observed that the flattening effect phenomenon is very reduced by applying the proposed asymmetric turbo codes. It gains respectively 1.7dB ~2.5dB and 2.0dB~2.5dB SNR improvements in the case of short frame(128, 256) and large frame(512, 1024) size for the BER $10_{-4}$>/TEX> region.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.156-163
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• 2012

Recently, Information Hiding Technology are becoming increasingly demanding in the field of international security, military and medical image This paper proposes data hiding technique utilizing parity checker for gray level image. many researches have been adopted LSB substitution and XOR operation in the field of steganography for the low complexity, high embedding capacity and high image quality. But, LSB substitution methods are not secure through it's naive mechanism even though it achieves high embedding capacity. Proposed method replaces LSB of each pixel with XOR(between the parity check bit of other 7 MSBs and 1 Secret bit) within one pixel. As a result, stego-image(that is, steganogram) doesn't result in high image degradation. Eavesdropper couldn't easily detect the message embedding. This approach is applying the concept of symmetric-key encryption protocol onto steganography. Furthermore, 1bit of symmetric-key is generated by the self-reference of each pixel. Proposed method provide more 25% embedding rate against existing XOR operation-based methods and show the effect of the reversal rate of LSB about 2% improvement.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.61-68
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• 2008

In this paper, we propose an efficient hardware architecture and algorithm to increase an encoding process rate and implement a hardware for CABAC (Context Adaptive Binary Arithmetic Coding) which is used with one of the entropy coding ways for the latest video compression technique, H.264/AVC (Advanced Video Coding). CABAC typically provides a better high compression performance maximum 15% compared with CAVLC. However, the complexity of operation of CABAC is significantly higher than the CAVLC. Because of complicated data dependency during the encoding process, the complexity of operation is higher. Therefore, various architectures were proposed to reduce an amount of operation. However, they have still latency on account of complicated data dependency. The proposed architecture has two techniques to implement efficient pipeline architecture. The one is quick calculation of 7, 8th bits used to calculate a probability is the first step in Binary arithmetic coding. The other is one step reduced pipeline arcbitecture when the type of the encoded symbols is MPS. By adopting these two techniques, the required processing time was reduced about 27-29% compared with previous architectures. It is designed in a hardware description language and total logic gate count is 19K using 0.18um standard cell library.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.12
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• pp.67-75
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• 2016

DNA computing technology makes the interests on DNA storage and DNA watermarking / steganography that use the DNA information as a newly medium. DNA watermarking that embeds the external watermark into DNA information without the biological mutation needs the reversibility for the perfect recovery of host DNA, the continuous embedding and detecting processing, and the mutation analysis by the watermark. In this paper, we propose a reversible DNA watermarking based on circular histogram shifting of DNA code values with the prevention of false start codon, the preservation of DNA sequence length, and the high watermark capacity, and the blind detection. Our method has the following features. The first is to encode nucleotide bases of 4-character variable to integer code values by code order. It makes the signal processing of DNA sequence easy. The second is to embed the multiple bits of watermark into -order coded value by using circular histogram shifting. The third is to check the possibility of false start codon in the inter or intra code values. Experimental results verified the our method has higher watermark capacity 0.11~0.50 bpn than conventional methods and also the false start codon has not happened in our method.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.43 no.1 s.307
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• pp.27-38
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• 2006

The main purpose of rate control is to achieve the highest video quality when bandwidth or storage capacity is limited. For this purpose, we need a rate control algorithm which is adaptively controlled by the motion information of sequences, scene change, buffer capacity and time-varing bandwitdh channels. A rate-control method in the encoder requires the accurate estimation of target bit for each frame and the low end-to-end delay for transmitting video data by intelligent selection of encoding parameters. In this paper, we suggest three kinds of linear relation in the encoder to satisfy the characteristics of rate control. The first relation is that between the percentage of zero quantized transformed coefficients(p) and coded bits. Second relation is that between the PSNR of encoded frame and its Quantization parameter(QP). Finally, we can find out a linear approximation between QP and p. According to the experimental analysis, the proposed method results in an efficient rate control in terms of the bit estimation, the buffer capacity, and PSNR compared with the existing rate control in the H.264 JM 9.3.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.3
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• pp.61-71
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• 2014

As the occupancy rate of the flash memory increases in the storage media market for the embedded system and the semi-conductor industry grows, the demand and supply of flash memory is increasing by a big margin. They are especially used in large quantity in the smart phones, tablets, PC, SSD and Soc(System on Chip) etc. The flash memory is divided into the NOR type and NAND type according to the cell arrangement structure and the NAND type is divided into the SLC(Single Level Cell) and MLC(Multi Level Cell) according to the number of bits that can be stored in each cell. Many tests have been performed on NOR type such as BIST(Bulit-In Self Test) and BIRA(Bulit-In Redundancy Analysis) etc, but there is little study on the NAND type. For the case of the existing BIST, the test can be proceeded using external equipments like ATE of high price. However, this paper is an attempt for the improvement of credibility and harvest rate of the system by proposing the BIST for the MLC NAND type flash memory of Finite State Machine structure on which the pattern test can be performed without external equipment since the necessary patterns are embedded in the interior and which uses the MLC NAND March(x) algorithm and pattern which had been proposed for the MLC NAND type flash memory.

• Journal of Periodontal and Implant Science
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• v.37 no.1
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• pp.65-75
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• 2007

In this study, author examined the effect of the concentration of the inorganic polyphosphate on the process of the bone regeneration by using the 6 weeks old rabbit with the weight of 2.0kg in average. we performed the experiment by using TR-eITFE membrane filled with collagen immersed with 1%, 2%, and 4% of inorganic polyphosphate, respectively, after removing the proper sized cort-ical bones from the calvaria of rabbit. The experimental results were compared with the one of the following four groups: The control group for membrane only, experimental group I for membrane filled with collagen im-mersed with 1% of inorganic polyphosphate, experimental group II for membrane filled with collagen immerse with 2% of inorganic polyphosphate, experimental group III for membrane filled with colla-gen immersed with 4% of inorganic polyphosphate. The fragments of the tissue with membrane were obtained from each group of the sacrificed rab-bits for 4 or 8 weeks sustained after surgery, were then prestained and coated. New bone formation was assessed by histomorphometric and statistical analysis. We may draw the conclusions from these experiments as following: 1. Collagen was an excellent carrier with a minimal inflammatory reaction and sustaining the form. 2. The sample of the 8th week group has shown the best bone regeneration compared with the cases of all groups including the control group. 3. The samples of collagen immersed with 2% and 4% of inorganic polyphosphate have shown more bone regeneration relative to the sample of the 1% inorganic polyphosphate. 4. The new bone regeneration was shown actively in the group for membrane filled with collagen immersed with 4% of inorganic polyphosphate. With above results, it is strongly suggested the use of inorganic polyphosphate with vehicle under TR-eITFE membrane.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.10
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• pp.1071-1078
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• 2003

In this paper, the planar, compact, and broadband phased array antenna system for IMT-2000 applications has been investigated. Two methods far designing a low-cost and low-complex beam-farming network are proposed. First, a new compact and broadband phase shifter with continuously controlled phase bits is designed by using parallel coupled lines. Second, its equivalent phase delay line is suggested to be capable of replacing the complex phase shifter with a reference phase bit on a phased array antenna. For the purpose of achieving the broadband system, in addition to the broadband phase shifter, a wide-slot antenna with a ground reflector is utilized as an element antenna. Therefore, the phased array antenna system has achieved compact size, broad bandwidth, and wide steering angle, although it has low complexity and low fabrication cost. The 3${\times}$1 phased array antenna system has a compact size of 1.6 λ${\times}$ l.6 λ, which is the sufficient ground plane of the wide-slot antenna. Experimental results present that the S$\_$11/ has less than 15 dB within the band and its radiation patterns on an E-plane have the capability of steering an antenna beam from -29$^{\circ}$to +30$^{\circ}$.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.5
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• pp.24-32
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• 2017

In this paper, a low power 4th order delta-sigma modulator was designed with a high resolution of 12 bits or more for the biological signal processing. Using time-interleaving technique, 4th order delta-sigma modulator was designed with one operational amplifier. So power consumption can be reduced to 1/4 than a conventional structure. To operate stably in the big difference between the two capacitor for kT/C noise and chip size, the variable-stage amplifier was designed. In the first phase and second phase, the operational amplifier is operating in a 2-stage. In the third and fourth phase, the operational amplifier is operating in a 1-stage. This was significantly improved the stability of the modulator because the phase margin exists within 60~90deg. The proposed delta-sigma modulator is designed in a standard $0.18{\mu}m$ CMOS n-well 1 poly 6 Metal technology and dissipates the power of $354{\mu}W$ with supply voltage of 1.8V. The ENOB of 11.8bit and SNDR of 72.8dB at 250Hz input frequency and 256kHz sampling frequency. From measurement results FOM1 is calculated to 49.6pJ/step and FOM2 is calculated to 154.5dB.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.3 s.333
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• pp.25-32
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• 2005

In this papers, we first, therefore, designed VCO(voltage controlled oscillator) that is composed of the dielectric resonator and the varactor diode, and then designed and fabricated PLDRO(phase locked dielectric resonator oscillator) that is combined with the sampling phase detector and loop filter. The measured results of the fabricated PLDRO at 12.05 [GHz] show the output power is 13.54 [dBm], frequency tuning range approximately +/- 7.5 [MHz], and Power variation over the tuning range less than 0.2 [dB], respectively. The phase noise which effects on bits error rate in digital communication is obtained with -114.5 [dBc/Hz] at 100 [KHz] offset from carrier, and The second harmonic suppression is less than -41.49 [dBc]. These measured results are found to be more improved than those of VCO without adopting PLL, and the phase noise and power variation performance characteristics show the better performances than those of conventional PLL.