• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.34-41
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• 2007

We popose a programmed on-line to FSM-based Programmable BIST(Buit-In Self-Test) with selected command, to select a test algorithm from a predetermined set of algorithms that are built in the Flash memory BIST. Thus, the proposed scheme greatly simplifies the testing process. Besides, the proposed FSM-based Programmable BIST is more efficient in terms of circuit size and test data to be applied, and it requires less time to configure the Flash memory BIST. We also will develop a programmable Flash memory BIST generator that automatically produces Verilog code of the proposed BIST architecture for a given set of test algorithms. If experiment the proposed method, the proposed method will achieves a good flexibility with smaller circuit size compared with previous methods.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.8
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• pp.1705-1712
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• 2004

This paper presents a new low-cost RF Built-In Self-Test (BIST) circuit for measuring transducer voltage gain, noise figure and input impedance of 5.25GHz low noise amplifier (LNA). The BIST circuit is designed using 0.18${\mu}{\textrm}{m}$ SiGe technology. The test technique utilizes input impedance matching and output transient voltage measurements. The technique is simple and inexpensive. Total chip size has additional area of about 18% for BIST circuit.

• The Transactions of the Korea Information Processing Society
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• v.4 no.7
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• pp.1900-1906
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• 1997

In this paper, the efficient BILBO(named EBILBO) is designed for BIST that is able to batch the testing when circuit is designed on FPGA. The proposed algorithm of batch testing is able to test the normal operation speed with one-pin-count that can control all part of large and complex circuit. PRTPG is used for the test pattern and MISR is used for PSA. The proposed algorithm of batch testing is VHDL coding on behavioral description, so it is easily modified the model of test pattern generation, signature analysis and compression. The EBILBO's area and the performance of designed BIST are evaluated with ISCAS89 benchmark circuit on FPGA. In circuit with above 600 cells, it is shown that area is reduced below 30%, test pattern is flexibly generated about 500K and the fault coverage is from 88.3% to 100%. EBILBO for the proposed batch testing BIST is able to execute concurrently normal and test mode operation in real time to the number of $s+n+(2^s/2^p-1)$ clock(where, in CUT, # of PI;n, # of register, p is order # of polynomial). The proposed algorithm coded with VHDL is made of library, then it well be widely applied to DFT that satisfy the design and test field on sme time.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1117-1120
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• 1998

BIST architecture and circuit design are presented for the self-test of various datapath megacells including embedded SRAM, barrel shifter, adder and multiplier. The BIST architecture is composed of VCO, ROM, comparator and otehr control logic to measure the megacell' performance up to 300MHz. PC interface and control logic are also implemented to perform the manual testing of each megacell with various test patterns. The control logic was designed using VHDL and its circuit is synthesized using Synopsys for $0.6\mu$ 1-poly, 3-matal CMOS technology.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.723-728
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• 1999

In this paper, we designed a Circular Path Built-In Self Test circuit and embedded it into a simple 8-bit microprocessor. Register cells of the microprocessor have been modified into Circular Path register cells and each register cells have been connected to form a scan chain. A BIST controller has been designed for controlling BIST operations and its operation has been verified through simulation. The BIST circuit described in this paper has increased size overhead of the microprocessor by 29.8% and delay time in the longest delay path from clock input to output by 2.9㎱.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.6
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• pp.322-329
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• 2000

BIST(Built-in Self Test) has been considered as the most promising DFT(design-for-test) scheme for the present and future test strategy. The most serious problem in applying BIST(Built-in Self Test) into a large circuit is the excessive increase in test time. This paper is focused on this problem. We proposed a new BIST construction scheme which uses a parallel divide-and-conquer method. The circuit division is performed with respect to some internal nodes called test points. The test points are selected by considering the nodal connectivity of the circuit rather than the testability of each node. The test patterns are generated by only one linear feedback shift register(LFSR) and they are shared by all the divided circuits. Thus, the test for each divided circuit is performed in parallel. Test responses are collected from the test point as well as the primary outputs. Even though the divide-and-conquer scheme is used and test patterns are generated in one LFSR, the proposed scheme does not lose its pseudo-exhaustive property. We proposed a selection procedure to find the test points and it was implemented with C/C++ language. Several example circuits were applied to this procedure and the results showed that test time was reduced upto 1/2151 but the increase in the hardware overhead or the delay increase was not much high. Because the proposed scheme showed a tendency that the increasing rates in hardware overhead and delay overhead were less than that in test time reduction as the size of circuit increases, it is expected to be used efficiently for large circuits as VLSI and ULSI.

• Proceedings of the IEEK Conference
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• 2003.11b
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• pp.27-30
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• 2003

The recent technology developments introduce new difficulties into the test process by the increased complexity of the chip. Most widely used method for testing high complexity and embedded systems is built-in self-test(BIST). In this paper, we describe 5-stage pipeline system as circuit under testing(CUT) and proposed a BIST scheme for the hazard detection unit of the pipeline system. The proposed BIST scheme can generate sequential instruction sets by pseudo-random pattern generator that can detect all hazard issues and compare the expected hazard signals with those of the pipelined system. Although BIST schemes require additional area in the system, it proves to provide a low-cost test solution and significantly reduce the test time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.8
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• pp.86-96
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• 2000

The representative area among the ones whose cost increases as the integration ratio increases is the test area. As the relative cost of hardware decreases, the BIST method has been focued on as the future-oriented test method. The biggest drawback of it is the increasing test time to obtain the acceptable fault coverage. This paper proposed a BIST implementation method to reduce the test times. This method uses an input grouping and test point insertion method, in which the definition of test point is different from the previous one. That is, the test points are defined on the basis of the internal nodes which are the reference points of the input grouping and are merging points of the grouped signals. The main algorithms in the proposed method were implemented with C-language, and various circuits were used to apply the proposed method for experiment. The results showed that the test time could be reduced to at most $1/2^{40}$ of the pseudo-random pattern case and the fault coverage were also increased compared with the conventional BIST method. The relative hardware overhead of the proposed method to the circuit under test decreases as th e size of the circuit to be tested increases, and the delay overhead by the BIST utility is negligible compared to that of the original circuit. That means, the proposed method can be applied efficiently to large VLSI circuits.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.6 s.336
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• pp.1-8
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• 2005

This paper presents a new low-cost fault-based Built-In Self-Test (BIST) scheme and technique for 1.8GHz RF receiver front end. The technique utilizes input impedance matching measurement. The BIST block and RF receiver front end are designed using 0.25m CMOS technology on a single chip. The technique is simple and inexpensive. The overhead of the BIST circuit is approximately $10\%$ of the total area of the RF front end.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.12
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• pp.1022-1032
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• 2002

A multibit DRAM BIST methodology reducing redundancy programming overhead has been proposed. It is capable of counting and locating faulty bits simultaneously with the test. If DRAM cells are composed of n blocks generally, the proposed BIST can detect the state of no error, the location of faulty bit block if there is one error and the existence of errors in more than two blocks, which are n + 2 states totally, with only n comparators and an 3 state encoder. Based on the proposed BIST methodology, the testing scheme which can detect the number and locations of faulty bits with the errors in two or more blocks, can be easily implemented. Based on performance evaluation, the test and redundancy programming time of 64MEG DRAM with 8 blocks is reduced by 1/750 times with 0.115% circuit overhead.