• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.11C
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• pp.712-719
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• 2011

In this paper, we analyzed the performance of soft decision e-BCH codes which presented in DVB-RCS NG system. However, the performance of soft-decision decoding for e-BCH is not much improved as to increase the iterations. Therefore this paper proposed rate-compatible TPC which makes various coding rates by zero padding the row and/or column to adapt next generation (NG) DVB-RCS system. And so we proposed new model of extended BCH code and researches how to develop performance of extended BCH code.

• Journal of Korea Multimedia Society
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• v.7 no.1
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• pp.73-79
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• 2004

In this paper, we propose an efficient soft decision decoding algorithm for linear block codes. A conventional soft decision decoder have to invoke a hard decision decoder several times to estimate its soft decision values. However, in this method, we may not have candidate codewords, thus it is very difficult to produce soft decision values. We solve this problem by introducing an efficient algorithm to search candidate codewords. By using this, we can highly reduce the cases we cannot find candidate codewords. We estimate the performance of the proposed algorithm by using the computer simulations. The simulation is performed for binary (63, 36) BCH code in fading channel.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.3
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• pp.309-315
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• 1998

This paper is analyzed the performance of coded MC-CDMA system using the multi-carrier with narrow band that is suggested to solve ISI and ICI of DS-CDMA system. In this paper, considered channel model is indoor mobile radio communication environment with Rician fading distribution and fading of multi-carrier have mutual independent characteristics. For the performance analysis of MC-CDMA system, first, bit error probability of uncoded system is simulated in the reverse and forward Rician channels. And then, it is simulated that bit error probability of coded MC-CDMA system for users, multicarriers and SNR, using (7,4) Hamming code, (15,7) BCH code and 1/2-convolutional code with 7 constraint length.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.7
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• pp.1118-1130
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• 1999

In this paper, error performance of DS/FH CDMA system has been analyzed in a radio channel which is characterized by near-far problem and multi-path fading. The DS/FH CDMA system adopts Maximum Ratio Combining(MRC) diversity and BCH(Bose-Chau dhuri-Hocquenghem) coding techniques to enhance system performance. Using the derived error probability equation, the error performance of DS/FH CDMA system has been evaluated and shown in figures to discuss as a function of PN code length(N), hopping rate(q), number of diversity branch(M), coding rate($\gamma$) and bit energy per noise power ratio ${E_b/N_o}$. The results show that DS/FH system is more effective to restrain the affection of near-far problem and multi-path fading than DS system. And there is a substantial enhancement in performance by employing an MRC diversity or BCH coding techniques. Consequently, we expected that proposed system structure is reliable to the voice communication system in near-far problem and multi-path fading channel.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.635-637
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• 2002

본 논문에서는 차세대이동통신에서 고속·고품질 전송을 실현하기 위해, 전송환경에 맞게 최적의 변조 다치 수를 선택하는 적응변조방식에 에러 정정 부호기법을 제안하였다. 고속ㆍ고품질화의 한 방법으로서, 에러 정정 부호를 적응한 시스템을 생각할 수 있는데, 본 논문에서 방식은 변조 파라미터가 변화하는 것에 의해 적응변조방식에 효과적인 BCH 부호 기법 및 RS 부호 기법을 적용한 경우의 전송 품질을 검토하였다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.6 no.1
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• pp.53-60
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• 1996

오증 요소로부터 오류위치다항식의 계수를 계산함으로서 (23,12) Golay 부호를 복호할 수 있는 대수적 복호법이 최근 증명되었다. GF(2)상에서의 3중 오류정정 BCH부호의 복호법을 이 부호에 완벽하게 적용하여 해석하는 것을 소개한다. 그리고 GF(2)에 대한 최적의 정규기저를 구하여 이를 유한체 연산에 적용하며 단계별로 복호 회로의 구성을 제시한다. 이는 기존의 복호기보다 논리회로적으로 간단하며, 복호된 정보를 얻기까지 35번의 치환이 필요하다.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.140-148
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• 2013

This paper presents a iterative Bose-Chaudhuri-hocquenghem (i-BCH) code and its high-speed decoder architecture for 100 Gb/s optical communications. The proposed architecture features a very high data processing rate as well as excellent error correction capability. The proposed 6-iteration i-BCH code structure with interleaving method allows the decoder to achieve 9.34 dB net coding gain performance at $10^{-15}$ decoder output bit error rate to compensate for serious transmission quality degradation. The proposed high-speed i-BCH decoder architecture is synthesized using a 90-nm CMOS technology. It can operate at a clock frequency of 430 MHz and achieve a data processing rate of 100 Gb/s. Thus, it has potential applications in next generation forward error correction (FEC) schemes for 100 Gb/s optical communications.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2004.10a
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• pp.485-488
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• 2004

본 논문에서는 OFDM(Orthogonal Frequency Division Multiplexing ：직교 주파수 분할 다중화) 전송방식을 사용한 시스템에서 주파수 옵셋으로 인한 동기 오차의 발생이 수신시스템에 미치는 영향을 분석하고 성능 개선기법으로 BCH부호기법을 적용하여 수신성능의 개선정도를 분석하였다. 결과에 의하면, BCH부호기법을 사용함으로써 T$_{s}$ f=0.02일 때 약 2dB의 BER 개선을 보였고, $\alpha$의 영향을 적게 받음을 알 수 있었고, T$_{s}$ f=0.05일 경우는 가드 인터벌 비율$\alpha$가 증가함에 따라 5dB이상의 BER 개선을 보이나 $\alpha$가 0.25이상에서는 여전히 요구되는 기준 BER를 만족하지 못함을 알 수 있었다. 또한, 낮은 수신전력(10dB)에서는 가드인터벌 비율의 변화보다는 주파수 옵셋량이 시스템 성능에 영향을 미침을 알 수 있고, 높은 수신전력에서는 (20dB) 주파수 옵셋량에 대해서는 강인한 성능을 보이지만 가드 인터벌 비율의 증가에 따라 BER 특성이 열화되는 것을 알 수 있었다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.41-47
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• 2010

This paper has proposed parallel BCH, one of error correction coding methods which has been used to NAND flash memory for SSD(solid state disk). To alter error correction capability, the proposed design improved reliability on data block has higher error rate as used frequency increasingly. Decoding parallel process bit width is as two times as encoding parallel process bit width, that could reduce decoding processing time, accordingly resulting in one half reduction over conventional ECC.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.2
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• pp.333-340
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• 2018

This paper introduces a BCH code decoder using parallel CRC(: Cyclic Redundancy Check) generation. Using a conventional parallel syndrome generator with a LFSR(: Linear Feedback Shift Register), it takes up a lot of space for a short code. The proposed decoder uses the parallel CRC method that is widely used to compute the checksum. This scheme optimizes the a syndrome generator in the decoder by eliminating redundant xor operation compared with the parallel LFSR and thus minimizes chip area and propagation delay. In simulation results, the proposed decoder has accomplished propagation delay reduction of 2.01 ns as compared to the conventional scheme. The proposed decoder has been designed and synthesized in $0.35-{\mu}m$ CMOS process.