• Journal of electromagnetic engineering and science
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• v.11 no.2
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• pp.105-112
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• 2011

In phase-locked frequency synthesizers, a fast-lock technique is frequently employed to overcome the trade-off between a lock-time and a spurious response. The function of fast-lock in a conventional PLL (Phased Lock Loop) IC (Integrated Circuit) is limited by a factor of 16, which is usually implemented by a scaling of charge pumper, and consequently a lock time improvement of a factor of 4 is possible using the conventional PLL IC. In this paper, we propose a novel external active fast-lock loop filter. The proposed loop filter provides, conceptually, an unlimited scaling of charge pumper current, and can overcome conventional trade-off between lock-time and spur suppression. To demonstrate the validity of our proposed loop-filter, we fabricated an X-band frequency synthesizer using the proposed loop filter. The loop filter in the synthesizer is designed to have a loop bandwidth of 100 kHz in the fast-lock mode and a loop bandwidth of 5 kHz in the normal mode, which corresponds to a charge pumper current change ratio of 400. The X-band synthesizer shows successful performance of a lock-time of below 10 ${\mu}sec$ and reference spur suppression below -64 dBc.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.1
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• pp.77-88
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• 2000

In this paper, the 3-mode variable gain high power amplifier for a transmitter of INMARSAT-B operating at L-band(1626.5-1646.5 MHz) was developed. This SSPA can amplify 42 dBm in high power mode, 38 dBm in medium power mode and 36 dBm in low power mode for INMARSAT-B. The allowable errol sets +1 dBm as the upper limit and -2 dBm as the lower limit, respectively. To simplify the fabrication process, the whole system is designed by two parts composed of a driving amplifier and a high power amplifier. The HP's MGA-64135 and Motorola's MRF-6401 were used for driving amplifier, and the ERICSSON's PTE-10114 and PTF-10021 for the high power amplifier. The SSPA was fabricated by the RP circuits, the temperature compensation circuits and 3-mode variable gain control circuits and 20 dB parallel coupled-line directional coupler in aluminum housing. In addition, the gain control method was proposed by digital attenuator for 3-mode amplifier. Then il has been experimentally verified that the gain is controlled for single tone signal as well as two tone signals. In this case, the SSPA detects the output power by 20 dB parallel coupled-line directional coupler and phase non-splitter amplifier. The realized SSPA has 41.6 dB, 37.6 dB and 33.2 dB for small signal gain within 20 MHz bandwidth, and the VSWR of input and output port is less than 1.3:1. The minimum value of the 1 dB compression point gets more than 12 dBm for 3-mode variable gain high power amplifier. A typical two tone intermodulation point has 36.5 dBc maximum which is single carrier backed off 3 dB from 1 dB compression point. The maximum output power of 43 dBm was achieved at the 1636.5 MHz. These results reveal a high power of 20 Watt, which was the design target.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.9 no.4
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• pp.55-61
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• 1995

Variable structure control (VSC) can be used for the control of power plants required stability and robustness such as elevator control. It has no overshoot and is insensitive to parameter variations and disturbances in the sliding mode where the system structure is changed with the sliding surface in the center. But in the real system, VSC has a high frequency chattering which has a bad influence upon the control system proformances. In this paper, to alleviate the high frequency chattering, a binary controller (BC) with inertial type external loop is implemented by DSP and applied to position control of brushless DC motor. Binary controller has external loop to generate the continuous control input with the flexible variation of primary loop gain. Thus it has the property of chattering alleviation in addition to advantages of the conventional variable structure control.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.845-848
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• 2005

This paper describes a 4.224GHz CMOS charge pump PLL for Mode 1 MB-OFDM UWB hopping carrier generation. It includes a qudrature VCO of which the frequency range is from 3.98GHz to 4.47GHz(@ 0.4 to 1.5 V), a divider, a PFD, a loop filter, a charge pump, and a lock detector. Designed in a 0.18um CMOS technology, the PLL draws 6.6mA from a 1.8V supply. The phase noise of the designed VCO is -133dBc/Hz@3MHz.

• KIEE International Transactions on Electrophysics and Applications
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• v.4C no.6
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• pp.272-275
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• 2004

A balanced single side-band (SSB) mixer employing a sub-harmonic configuration is designed for up and down conversions in K-band. The designed mixer uses anti-parallel diode (APD) pairs to effectively eliminate even harmonics of the local oscillator (LO) spurious signal. To reduce the odd harmonics of LO at the RF port, we employ a balanced configuration for LO. The fabricated chip shows 12$\pm$2dB of conversion loss and image-rejection ratio of about 20dB for down conversion at RF frequencies of 24-27.5GHz. As an up-conversion mode, the designed chip shows 12dB of conversion loss and image-rejection ratio of 20 ～ 25 dB at RF frequencies of 25 to 27GHz. The odd harmonics of the LO are measured below -37dBc.

• Current Optics and Photonics
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• v.6 no.6
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• pp.634-641
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• 2022

A frequency stable and tunable optoelectronic oscillator (OEO) incorporating an optical phase shifter and a phase-shifted fiber Bragg grating (PS-FBG) is designed and analyzed. The frequency tunability of the OEO can be realized by using a tunable microwave photonic bandpass filter consisting of a PS-FBG, a phase modulator. The optical phase compensation loop is used to compensate for the phase variations of the RF signal from the OEO by adjusting an optical phase shifter. Simulation results demonstrate that the output RF signals of the OEO can be tuned in a frequency range of 118 MHz to 24.092 GHz. When the ambient temperature fluctuates within ±3.9 ℃, the frequency drifts of the output RF signals are less than 68 Hz, the side-mode suppression ratios are more than 69.39 dB, and the phase noise is less than -92.49 dBc/Hz at a 10 kHz offset frequency.

• KOREAN JOURNAL OF CROP SCIENCE
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• v.58 no.2
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• pp.149-160
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• 2013

The objective of present study was to simultaneously isolate of isoflavone and soyasaponin compounds from the germ of soybean seeds. Soy germ flours were defatted with hexane for 48h at room temperature, and methanolic extracts were prepared using reflux apparatus at $90^{\circ}C$ for 6h, two times. After extraction, extracts were separated with preparative RP-$C_{18}$ packing column ($125{\AA}$, $55-105{\mu}m$, $40{\times}150mm$), and collected 52 fractions were identified with TLC plate (Kieselgel 60 F-254) and HPLC, respectively. Among the identified isoflavone and soyasaponin fractions, isoflavone fractions were re-separated using a recycling HPLC with gel permeation column (Jaigel-W252, $20{\times}500mm$). Final fractions were air-dried, and the purified compounds of two isoflavones (ISF-1-1, ISF-1-2) and four soyasaponins (SAP-1, SAP-2, SAP-3, SAP-4) were obtained. Two isoflavone compounds (ISF-1-1, ISF-1-2) were acid-hydrolyzed for the identification of their aglycones, and confirmed by comparing with 12 types of isoflavone isomers. While the four kinds of soyasaponins were identified by using a micro Q-TOF mass spectrometer in the ESI positive mode with capillary voltage of 4.5kV, and dry temperature of $200^{\circ}C$. Base on the obtained results, it was conclude that ISF-1-1 is the mixture isomers of daidzin (43.4%), glycitin (47.0%), and genistin (9.6%), but ISF-1-2 is the single compound of genistin (99.8% <). On the other hand, soyasaponin SAP-1 is the mixture compounds of soyasaponin A-group (Aa, Ab, Ac, Ae, Af); SAP-2 is soyasaponin B-group (Ba, Bb, Bc) and E-group (Bd, Be); SAP-3 is soyasaponin B-group (Ba, Bb, Bc), E-group (Bd, Be), and DDMP-group (${\beta}g$); SAP-4 is soyasaponin B-group (Ba, Bb, Bc), E-group (Bd, Be), and DDMP-group (${\beta}g$, ${\beta}a$), respectively.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.1
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• pp.17-24
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• 2014

In this paper, we analysed coupling coefficient between dielectric resonator of high dielectric constant and microstrip line to design for low phase noise dielectric resonator by direct coupling. Also we analysed phase noise of dielectric resonance oscillator with parallel feedback circuit to complement Q by high dielectric constant. We obtained a result from high-stability dielectric oscillator which is optimum designed through analysis of dielectric resonance oscillator phase noise and coupling coefficient. The result is that the phase noise was -83.3dBc/Hz@1KHz at 20.25GHz when we used about 3.6 coupling coefficient and ${\epsilon}_r$=30 dielectric resonator of 20.25GHz dielectric resonance oscillator. As a result, we suggested the direct-connect design method by frequency multiplication mode to prevent phase noise loss at K-Band.

• Journal of IKEEE
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• v.15 no.1
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• pp.29-36
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• 2011

Dithering scheme has been widely used to improve the resolution of DCO(Digitally Controlled Oscillator) in conventional ADPLLs(All Digital Phase Locked Loop). In this paper a new resolution improvement scheme is proposed where a simple DAC is employed to overcome the problems of dithering scheme. A 2.4GHz LC-based DCO has been designed in a $0.13{\mu}m$ CMOS process with an enhanced frequency resolution for wireless local area network applications. It has a frequency tuning range of 900MHz and a resolution of 58.8Hz. The frequencies are controled by varactors in coarse, fine, and DAC bank. The DAC bank consists of an inversion mode NMOS varactor. The other varactor banks consist of PMOS varactors. Each varactor bank is controlled by 8bit digital signal. The designed DCO exhibits a phase noise of -123.8dBc/Hz at 1MHz frequency offset. The DCO core consumes 4.2mA from 1.2V supply.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.7
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• pp.1543-1551
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• 2011

Dithering scheme has been widely used to improve the resolution of DCO(Digitally Controlled Oscillator) in conventional ADPLLs(All Digital Phase Locked Loop). In this paper a new resolution improvement scheme is proposed where a simple DAC(Digital-to-Analog Converter) is employed to overcome the problems of dithering scheme. The frequencies are controled by varactors in coarse, fine, and DAC bank. The DAC bank consists of an inversion mode NMOS varactor. The other varactor banks consist of PMOS varactors. Each varactor bank is controlled by 8bit digital signal. The proposed DCO has been designed in a $0.13{\mu}m$ CMOS process. Measurement results shows that the designed DCO oscillates in 2.8GHz~3.5GHz and has a frequency tuning range of 660MHz and a resolution of 73Hz at 2.8GHz band. The designed DCO exhibits a phase noise of -119dBc/Hz at lMHz frequency offset. The DCO core consumes 4.2mA from l.2V supply. The chip area is $1.3mm{\times}1.3mm$ including pads.