• Nuclear Engineering and Technology
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• v.44 no.8
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• pp.971-976
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• 2012

Silica-coated Au with Ag, Co, Cu, and Ir bimetallic radioisotope nanoparticles were synthesized by neutron irradiation, after coating $SiO_2$ onto the bimetallic particles by the sol-gel St$\ddot{o}$ber process. Bimetallic nanoparticles were synthesized by irradiating aqueous bimetallic ions at room temperature. Their shell and core diameters were recorded by TEM to be 100 - 112 nm and 20 - 50 nm, respectively. The bimetallic radioisotope nanoparticles' gamma spectra showed that they each contained two gamma-emitting nuclides. The nanoparticles could be used as radiotracers in petrochemical and refinery processes that involve temperatures that would decompose conventional organic radioactive labels.

• Resources Recycling
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• v.20 no.4
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• pp.58-64
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• 2011

Recovery of novel metals such as Au, Ag and Ni from wastes PCB was investigated by slag treatments. The CaO-$Al_2O_3$(-$SiO_2$) and CaO-$SiO_2$-$CaF_2$ slags were employed in the present study. The PCB/Cu ratio is recommended to be lower than unity. The use of CaO-$SiO_2$-$CaF_2$ slag provided the more higher yield of Au, Ag and Ni than the CaO-$Al_2O_3$(-$SiO_2$) slag did, which was mainly due to the lower melting point and the viscosity of $CaF_2$-containing slag. The terminal descending velocity of metal droplets in the slag phase increased with decreasing slag viscosity.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.3
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• pp.79-84
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• 2010

Formation of TSV (Through-Si-Via) with an Au seed layer and Cu filling to the via, simplification of bumping process for three dimensional stacking of Si dice were investigated. In order to produce the via holes, the Si wafer was etched by a DRIE (Deep Reactive Ion Etching) process using $SF_6$ and $C_4F_8$ plasmas alternately. The vias were 40 ${\mu}m$ in diameter, 80 ${\mu}m$ in depth, and were produced by etching for 1.92 ks. On the via side wall, a dielectric layer of $SiO_2$ was formed by thermal oxidation, and an adhesion layer of Ti, and a seed layer of Au were applied by sputtering. Electroplating with pulsed DC was applied to fill the via holes with Cu. The plating condition was at a forward pulse current density of 1000 mA/$dm^2$ for 5 s and a reverse pulse current density of 190 mA/$dm^2$ for 25 s. By using these parameters, sound Cu filling was obtained in the vias with a total plating time of 57.6 ks. Sn bumping was performed on the Cu plugs without lithography process. The bumps were produced on the Si die successfully by the simplified process without serious defect.

• Proceedings of the Korean Vacuum Society Conference
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• 1995.02a
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• pp.057-58
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• 1995

극소전자 디바이스의 고집적화에 의해 박막배선의 선폭은 0.5$mu extrm{m}$ 이하로 축소되고 있고 상대적으로 높은 전류밀도가 흐르게 된다. 높은 전류밀도하에서는 현재 일반적으로 사용되고 있는 Al을 기본으로 하는 박막배선에서의 electromigration에 의한 결함 발생 그리고 비교적 낮은 전기전도도가 심각한 문제점으로 제기된다. 본 연구에서는 Al과 고전기전도도 물질인 Ag, Cu, 그리고 Au 박막배선에 대해 electromigration에 대한 저항성, 즉 activation energy를 측정 비교함으로써 차세대 극소전자 디바이스를 위한 박막배선재료로서의 가능성을 알아보고자 한다. Electromigration test 및 activation energy를 구하기 위해 순수 Ag, Cu, Al, Au 박막배선을 0.05$\mu\textrm{m}$ 두께, 100$\mu\textrm{m}$ 선폭, 그리고 5000$\mu\textrm{m}$ 길이로 SiO2 열산화막 처리된 pp-Si(100) 기판 위에 진공 증착시켰다. 가속화 실험을 위해 인가된 d.c. 전류밀도는 2$\times$106A/$ extrm{cm}^2$ 이었고, Al과 Au에서는 6$\times$106A/$\textrm{cm}^2$이었다. 실온에서 24$0^{\circ}C$까지의 온도범위에서 d.c.인가후의 저항변화를 측정하여 Median-Time-to-Failure(MTF)를 구한 후 Black 방정식을 이용하여 activation energy를 측정하였다. Activation energy는 Cu가 1.34eV로서 가장 높게 나타났고 Au가 1.01eV, Al이 0.66eV, Ag가 0.29eV의 순으로 측정되었다. 따라서 Cu와 Au 박막배선의 경우 Al보다 electromigration에 대한 저항력이 강한 고활성화에너지 특성을 갖는 고전기전도도 재료로서 차세대 극소전자 디바이스를 위한 대체 박막배선재료로서의 가능성을 보인다.

• Economic and Environmental Geology
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• v.44 no.5
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• pp.359-372
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• 2011

TA26 seamount, which is located at south part of Tonga arc, occurs widely hydrothermal plume and is area that sampled hostrock, hydrothermal ore and hydrothermal alteration rock for this study. Hostrocks are basalt and basaltic andesite. Altered rocks by hydrothermal solution consists of plagioclase, pyroxene, pyrite, ilmenite, amorphous silica, barite, smectite, iron sulfates, Fe-Si sulfates and Fe silicates. Gains and losses of major, trace and rare earth elements during wallrock alteration suggest that $K_2O$(+0.04~+0.45 g), $SiO_2$(-6.52~+10.56 g), $H_2O$(-0.03~+6.04 g), $SO_4$(-0.46~+17.54 g), S(-0.46~+13.45 g), total S(-0.51~+16.93 g), Ba(-7.60~+185078.62 g), Sr(-36.18~+3033.08 g), Ag(+54.83 g), Au(+1467.49 g), As(-5.80~+1030.80 g), Cd(+249.78 g), Cu(-100.57~+1357.85 g), Pb(+4.91~+532.65 g), Sb(-0.32~+66.59 g), V(-113.58~+102.94 g) and Zn(-49.56~+14989.92 g) elements are enriched from hydrothermal solution. Therefore, gained(enriched) elements(($K_2O$, $H_2O$, $SO_4$, S, total S, Ba, Sr, Ag, Au, As, Cd, Cu, Pb, Sb, V, Zn) represent a potentially tools for exploration of sea-floor hydrothermal deposits from the Tonga arc.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.2
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• pp.37-41
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• 2017

Cuprous oxide ($Cu_2O$) is one of the potential candidates as an absorber layer in ultra-low-cost solar cells. $Cu_2O$ is highly desirable semiconducting oxide material for use in solar energy conversion due to its direct band gap ($E_g={\sim}2.1eV$) and high absorption coefficient that absorbs visible light of wavelength up to 650 nm. In addition, $Cu_2O$ has other several advantages such as non-toxicity, low cost and also can be prepared with simple and cheap methods on large scale. In this work, we deposited the $Cu_2O$ thin films by electrodeposition on gold coated $SiO_2/Si$ wafers. We changed the process conditions such as pH of the solution, applied potential on working electrode, and solution temperature. Finally, we confirmed the structural properties of the thin films by XRD and SEM.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2009.10a
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• pp.171-172
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• 2009

TSV(through via silicon)를 이용한 Via의 Cu 충전에서 Seed 층의 역할은 전류의 흐름을 가능하게 하는 중요한 역할을 하고 있다. Via에 각각 Ti/Au, Ti/Cu를 증착한 후 Ti/Cu가 Ti/Au를 대체 할 수 있는지를 알아보기 위해 먼저 실리콘 웨이퍼에 via를 형성하고, 형성된 via에 기능성 박막층으로 절연층(SiO2) 및 시드층을 형성하였다. 전해도금을 이용하여 Cu를 충전한 결과 Ti/Au 및 Ti/Cu를 증착한 두 시편 모두 via와 seed층 접합면에 박리 등의 결함이 없었고, via 내부 또한 void나 seam 등이 관찰되지 않고 우수하게 충전된 것을 확인할 수 있었다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.751-753
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• 2007

Organic field-effect transistors (OFETs) are of interest for use in widely area electronic applications. We fabricated a copper phthalocyanine (CuPc) based field-effect transistor with different metal electrode. The CuPc FET device was made a top-contact type and the substrate temperature was room temperature. The source and drain electrodes were used an Au and Al materials. The CuPc thickness was 40nm. and the channel length was $50{\mu}m$, channel width was 3mm. We observed a typical current-voltage (I-V) characteristics in CuPc FET with different electrode materials.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.3
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• pp.85-91
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• 1999

$H:LiNbO_3$ optical modulator with Cu/parylene electrode layer, which has a merits in the bandwidth, power consumption and fabrication conditions as compared with conventional Au/Cr/$SiO_2$, is proposed and fabricated. Analysis and design of optical modulator is performed by finite element calculation. Various unit processes for fabricating the proposed modulator, 1550nm $H:LiNbO_3$ optical waveguide, parylene buffer layer, and CPW Cu electrode, were developed, After dicing and end-face polishing of fabricated modulator chip, optical modulation responses as sawtooth electrical driving voltage has been measured at low frequencies. Properties of optical waveguide had not been changed before and after Cu/parylene electrode processes, which make confirm the reproducible fabrication of optical modulator.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.4
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• pp.49-53
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• 2011

High-speed Cu filling into a through-silicon-via (TSV) and simplification of bumping process by electroplating for three dimensional stacking of Si dice were investigated. The TSV was prepared on a Si wafer by deep reactive ion etching, and $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. In order to increase the filling rate of Cu into the via, a periodic-pulse-reverse wave current was applied to the Si chip during electroplating. In the bumping process, Sn-3.5Ag bumping was performed on the Cu plugs without lithography process. After electroplating, the cross sections of the vias and appearance of the bumps were observed by using a field emission scanning electron microscope. As a result, voids in the Cu-plugs were produced by via blocking around via opening and at the middle of the via when the vias were plated for 60 min at -9.66 $mA/cm^2$ and -7.71 $mA/cm^2$, respectively. The Cu plug with a void or a defect led to the production of imperfect Sn-Ag bump which was formed on the Cu-plug.