• Bulletin of the Korean Chemical Society
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• v.32 no.3
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• pp.880-884
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• 2011

ZnO nanorods were grown by hydrothermal method. Two kinds of seed layers, Au film and island seed layers were prepared to investigate the effect of seed layer on ZnO nanorods. The ZnO nanorod on Au island seed layer has more unifom diameter and higher density compared to that of ZnO nanorod on Au film seed layer. The ZnO nanorods on Au island seed layer were annealed at various temperatures ranging from 300 to $850^{\circ}C$. The pinholes at the surface of the ZnO nanorods is formed as the annealing temperature is increased. It is noted that the pyramid structure on the surface of ZnO nanorod is observed at $850^{\circ}C$. The intensity of ZnO (002) diffraction peak in X-ray diffraction pattern and intensity of near band edge emission (NBE) peak in photoluminescence (PL) are increased as the ZnO nanorods were annealed at the temperature of $300^{\circ}C$.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.354-354
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• 2012

In this study, we report the vertically aligned ZnO nanowires by using different type of Ga-doped ZnO (GZO) thin films as seed layers to investigate how the underlying GZO film micro structure affects the distribution of ZnO nanowires. Arrays of highly ordered ZnO nanowires have been synthesized on GZO thin film seed layer prepared on p-Si substrates ($7-13{\Omega}cm$) with utilize of a pulsed laser deposition (PLD). With the vapor-liquid-solid (VLS) growth process, the ZnO nanowire synthesis carries out no metal catalyst and is cost-effective; furthermore, The GZO seed layer facilitates the uniform growth of well-aligned ZnO nanowires. The influence of the growth temperature and various thickness of GZO seed layer have been analyzed. Crystallinity of grown seed layer was studied by X-Ray diffraction (XRD); diameter and morphology of ZnO nanowires on seed layer were investigated by field emission scanning electron microscopy (FE-SEM). Our results suggest that the GZO seed layer with high c-axis orientation, good crystallinity, and less lattice mismatch is key parameters to optimize the growth of well-aligned ZnO nanowire arrays.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2009.10a
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• pp.171-172
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• 2009

TSV(through via silicon)를 이용한 Via의 Cu 충전에서 Seed 층의 역할은 전류의 흐름을 가능하게 하는 중요한 역할을 하고 있다. Via에 각각 Ti/Au, Ti/Cu를 증착한 후 Ti/Cu가 Ti/Au를 대체 할 수 있는지를 알아보기 위해 먼저 실리콘 웨이퍼에 via를 형성하고, 형성된 via에 기능성 박막층으로 절연층(SiO2) 및 시드층을 형성하였다. 전해도금을 이용하여 Cu를 충전한 결과 Ti/Au 및 Ti/Cu를 증착한 두 시편 모두 via와 seed층 접합면에 박리 등의 결함이 없었고, via 내부 또한 void나 seam 등이 관찰되지 않고 우수하게 충전된 것을 확인할 수 있었다.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.3
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• pp.79-84
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• 2010

Formation of TSV (Through-Si-Via) with an Au seed layer and Cu filling to the via, simplification of bumping process for three dimensional stacking of Si dice were investigated. In order to produce the via holes, the Si wafer was etched by a DRIE (Deep Reactive Ion Etching) process using $SF_6$ and $C_4F_8$ plasmas alternately. The vias were 40 ${\mu}m$ in diameter, 80 ${\mu}m$ in depth, and were produced by etching for 1.92 ks. On the via side wall, a dielectric layer of $SiO_2$ was formed by thermal oxidation, and an adhesion layer of Ti, and a seed layer of Au were applied by sputtering. Electroplating with pulsed DC was applied to fill the via holes with Cu. The plating condition was at a forward pulse current density of 1000 mA/$dm^2$ for 5 s and a reverse pulse current density of 190 mA/$dm^2$ for 25 s. By using these parameters, sound Cu filling was obtained in the vias with a total plating time of 57.6 ks. Sn bumping was performed on the Cu plugs without lithography process. The bumps were produced on the Si die successfully by the simplified process without serious defect.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.4
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• pp.63-69
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• 2007

We investigated interconnection processes using Cu vias for MEMS sensor packages. Ag paste layer was formed on a glass substrate and used as a seed layer for electrodeposition of Cu vias after bonding a Si substrate with through-via holes. With applying electrodeposition current densities of $20mA/cm^2\;and\;30mA/cm^2$ at direct current mode to the Ag paste seed-layer, Cu vias of $200{\mu}m$ diameter and $350{\mu}m$ depth were formed successfully without electrodeposition defects. Interconnection processes for MEMS sensor packages could be accomplished with Ti/Cu/Ti line formation, Au pad electrodeposition, Sn solder electrodeposition and reflow process on the Si substrate where Cu vias were formed by Cu electrodeposition into through-via holes.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.243-243
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• 2009

Bi2O3 doped ZnO nanostructures structure were successfully synthesized by a thermal evaporatiion process and their structural characteristics were investigated. It is demonstrated that the growth condition such as the areal density, pretreatment of the substrates and growth temperature have great influence on the morphology and the alignment of the nanorods arrays. The density of Bi2O3 doped ZnO nanostructures is controlled by the gold (Au) nanoparticle density deposited on the silicon substrates. Relatively homogenous size and shape were observed by introducing gold(Au) seed-layer as nucleation centers on the substrates prior to the VLS reaction. The samples were characterized by X-ray diffraction, scanning electron microscopy.

• Proceedings of the KIEE Conference
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• 2003.10a
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• pp.297-299
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• 2003

In this paper, we present the fabrication of copper electrode array and test of electrochemical discharge machining for the fabrication of microholes on Borofloat33 glass. Copper electrode array is fabricated by the bonding of silicon upper substrate and lower substrate and copper electroplate. The silicon upper electrode having microholes fabricated by ICP-RIE is the mold of copper electroplate. The lower substrate is used as the seed layer for copper electroplate after Au - Au thermocompression bonding with the upper substrate.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.4
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• pp.361-364
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• 2008

Tips of probe card were fabricated using MEMS technology. P-type silicon wafer with $SiO_2$ layer was used as a substrate for fabricating the probe card. Ni-Cr and Au used as seed layer for electroplating Ni were deposited on the silicon wafer. Line patterns for probing devices were formed on silicon wafer by electroplating Ni through mold which formed by MEMS technology. Bridge structure was formed by wet-etching the silicon substrate. AZ-1512 photoresist was used for protection layer of back side and DNB-H100PL-40 photoresist was used for patterning of the front side. The mold with the thickness of $60{\mu}m$ was also formed using THB-120N photoresist and probe tip with thickness of $50{\mu}m$ was fabricated by electroplating process.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.209-209
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• 2010

금(Au) 또는 은(Ag) 금속 나노입자의 모양, 크기, 분포 상태를 조절하여 가시광선과 적외선, 자외선 영역에서 강한 표면 플라즈몬 효과을 이용할 수 있는데, 최근 이러한 금속 나노입자의 표면플라즈몬 효과를 이용하여 태양광 소자의 성능을 향상시키는 연구가 매우 활발하게 이루어지고 있다. 그 중, 높은 효율과 낮은 제작비용 그리고 간단한 공정과정의 장점을 갖고 있어서 크게 주목 받고 있는 염료감응태양전지에서도 금(Au) 또는 은(Ag) 금속 나노입자을 이용하기 위한 많은 연구가 진행되고 있다. 그 예로, Au가 코팅된 $TiO_2$ 기반의 염료감응태양전지구조를 제작하여, 입사된 빛이 표면플라즈몬 효과를 통해, Au에서 여기된 전자들이 Au/$TiO_2$ 사에의 schottky 장벽을 통과하여 $TiO_2$의 전도대 전자들의 밀도가 증가하여, charge carrier generating rate을 높여 소자의 광변환 효율의 향상을 증명하였다. 이에 본 연구에서는, $TiO_2$보다 높은 전자 이동도(mobility)와 직선통로(direct path way)의 장점을 갖고 있는 ZnO nanorod에서의 charge carrier generating rate을 높일 수 있도록, 비교적 가격이 저렴한 Ag nanoparticle을 코팅하였다. ZnO nanorod 제작은 낮은 온도에서 간단하게 성장시킬 수 있는 hydrothermal 방법을 이용하였다. 기판위에 RF magnetron 스퍼터를 이용하여 AZO seed layer를 증착한 후, zinc nitrate $Zn(NO_3)_2{\cdot}6H_2O$과 hexamethylentetramines (HMT)으로 혼합된 용액을 사용해 ZnO nanorods를 성장시켰다. 이 후, Ag를 형성할 수 있도록 열증기증착법을 이용하여 코팅하였다. Ag의 증착시간에 따른 ZnO nanorods에서의 코팅된 구조와 형태를 관찰하기 위해 field emission scanning electron microscopy (FE-SEM)을 이용하여 측정하였으며, 결정성을 조사하기 위해 X-ray diffraction (XRD)을 이용하여 분석하였다. 또한 입사된 빛에 의해, 여기된 ZnO 전도대 전자들이 다시 재결합을 통해 방출되는 photoluminescence 양을 scanning PL 장비를 통해 측정하여 Ag가 코팅된 ZnO nanorod의 광특성을 분석하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.377-377
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• 2012

반도체 물질로서 Zinc oxide (ZnO) nanorod (NR)는 Hydrothermal growth method로 제작 시 고가의 장비가 필요치 않기에 저비용 대면적 박막을 제작하는데 적합하지만 NR들의 array 조절과 각각의 rod와 전극 간의 연결에서 어려움을 가지고 있다. 최근 연구에서는 이러한 NR array 형상 조절과 소자의 성능 향상을 위하여 tilted sputtering method를 이용해 seed layer를 lateral 하게 형성하여 성장시켜 표면적을 극대화함으로서 응용되는 센서의 성능을 향상시키는 연구가 진행되고 있다. 본 연구에서는 이렇게 향상된 수평구조의 ZnO NR과 다양한 전극 금속 간의 schottky barrier의 높이 차이에 따라 sensitivity와 response time의 차이를 측정하였다. NR들을 전계방출형 전자현미경과 XRD로 분석 NR의 lateral structure 및 결정성을 확인하였다. 그리고 이렇게 형성한 NR을 소자화하여 Au, Ag, Al을 전극 금속물질로 사용한 경우에 대하여 sensing performance와 전극 금속의 schottky barrier의 상관관계를 확인하였다.