• The Journal of the Convergence on Culture Technology
• /
• v.7 no.1
• /
• pp.558-563
• /
• 2021

Quantum-Dot Cellular Automata is a next-generation nanocircular design technology that is drawing attention from many research organizations not only because it is possible to design efficient circuits by overcoming the physical size limitations of existing CMOS circuits, but also because of its energy-efficient features. In this paper, one of the existing digital circuits, T flip-flop circuit, is proposed using QCA. The previously proposed T flip-flops are designed based on the majority gate, so the circuits are complex and have long delays. Therefore, the design of the XOR gate-based T flip-flop using cell interaction reduces circuit complexity and minimizes latency. The proposed circuit is simulated using QCADesigner, and the performance is compared and analyzed with the existing proposed circuits.

• The Journal of the Acoustical Society of Korea
• /
• v.42 no.6
• /
• pp.544-551
• /
• 2023

Speech enhancement used to improve the perceptual quality and intelligibility of noise speech has been studied as a method using a complex-valued spectrum that can improve both magnitude and phase in a method using a magnitude spectrum. In this paper, a study was conducted on how to apply attention mechanism to complex-valued spectrum-based speech enhancement systems to further improve the intelligibility and quality of noise speech. The attention is performed based on additive attention and allows the attention weight to be calculated in consideration of the complex-valued spectrum. In addition, the global average pooling was used to consider the importance of the feature map. Complex-valued spectrum-based speech enhancement was performed based on the Deep Complex U-Net (DCUNET) model, and additive attention was conducted based on the proposed method in the Attention U-Net model. The results of the experiments on noise speech in a living room environment showed that the proposed method is improved performance over the baseline model according to evaluation metrics such as Source to Distortion Ratio (SDR), Perceptual Evaluation of Speech Quality (PESQ), and Short Time Object Intelligence (STOI), and consistently improved performance across various background noise environments and low Signal-to-Noise Ratio (SNR) conditions. Through this, the proposed speech enhancement system demonstrated its effectiveness in improving the intelligibility and quality of noisy speech.

• Annual Conference on Human and Language Technology
• /
• 2017.10a
• /
• pp.35-40
• /
• 2017

기계 독해(Machine reading comprehension)는 주어진 문맥을 이해하고, 질문에 적합한 답을 문맥 내에서 찾는 문제이다. Simple Recurrent Unit (SRU)은 Gated Recurrent Unit (GRU)등과 같이 neural gate를 이용하여 Recurrent Neural Network (RNN)에서 발생하는 vanishing gradient problem을 해결하고, gate 입력에서 이전 hidden state를 제거하여 GRU보다 속도를 향상시킨 모델이며, Self-matching Network는 R-Net 모델에서 사용된 것으로, 자기 자신의 RNN sequence에 대하여 어텐션 가중치 (attention weight)를 계산하여 비슷한 의미 문맥 정보를 볼 수 있기 때문에 상호참조해결과 유사한 효과를 볼 수 있다. 본 논문에서는 한국어 기계 독해 데이터 셋을 구축하고, 여러 층의 SRU를 이용한 Encoder에 Self-matching layer를 추가한 $S^2$-Net 모델을 제안한다. 실험 결과, 본 논문에서 제안한 $S^2$-Net 모델이 한국어 기계 독해 데이터 셋에서 EM 65.84%, F1 78.98%의 성능을 보였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2009.06a
• /
• pp.44-44
• /
• 2009

Recently, transparent ZnO-based TFTs have attracted much attention for flexible displays because they can be fabricated on plastic substrates at low temperature. We report the fabrication and characteristics of ZnO channel layers(ZnO TFTs) having different channel thicknesses. The ZnO film were deposited as active channel layers on $Si_3N_4/Ti/SiO_2p$-Si substrates by rf magnetron sputtering at $100\;^{\circ}C$ without additional annealing. Also the Zno thin films deposited at oxygen partial pressures of 40%. ZnO TFTs using a bottom-gate configuration were investigated. The $Si_3N_4$ film were deposited as gate insulator by PE-CVD at $15\;^{\circ}C$. All Processes were processed below $150^{\circ}C$ which is optimal temperature for flexible display and were used dry etching method.

• Journal of Power Electronics
• /
• v.11 no.2
• /
• pp.218-227
• /
• 2011

The subject of variable step size maximum power point tracking (MPPT) algorithms has been addressed in the literature. However, most of the addressed algorithms tune the variable step size according to two variables: the photovoltaic (PV) array voltage ($V_{PV}$) and the PV array current ($I_{PV}$). Therefore, both the PV array current and voltage have to be measured. Recently, maximum power point trackers that arc based on a single variable ($I_{PV}$ or $V_{PV}$) have received a great deal of attention due to their simplicity and ease of implementation, when compared to other tracking techniques. In this paper, two methods have been proposed to design a variable step size MPPT algorithm using only a single current sensor for stand-alone battery storage PV systems. These methods utilize only the relationship between the PV array measured current and the converter duty cycle (D) to automatically adapt the step change in the duty cycle to reach the maximum power point (MPP) of the PV array. Detailed analyses and flowcharts of the proposed methods are included. Moreover, a comparison has been made between the proposed methods to investigate their performance in the transient and steady states. Finally, experimental results with field programmable gate arrays (FPGAs) are presented to verify the performance of the proposed methods.

• Journal of the Korean Vacuum Society
• /
• v.7 no.3
• /
• pp.208-213
• /
• 1998

Silicidation of the Co/Ti/Si bilayer system in which Ti is used as epitaxy promoter for $CoSi_2$has recently received much attention. The Co/Ti bilayer on the spacer oxide of gate electrode must be thermally stable at high temperatures for a salicide transistor to be fabricated successfully. In the $SiO_2$substrate was rapid-thermal annealed. The Sheet resistances of the Co/Ti bilayer increased substantially after annealing at $600^{\circ}C$, which is due to the agglomeration of the Co layer to reduce the interface energy between the Co layer and the $SiO_2$substrate. In the bilayer system insulating Ti oxide stoichiometric Ti oxide and silicide were not found after annealing.

• 한국어정보학회:학술대회논문집
• /
• 2017.10a
• /
• pp.35-40
• /
• 2017

기계 독해(Machine reading comprehension)는 주어진 문맥을 이해하고, 질문에 적합한 답을 문맥 내에서 찾는 문제이다. Simple Recurrent Unit (SRU)은 Gated Recurrent Unit (GRU)등과 같이 neural gate를 이용하여 Recurrent Neural Network (RNN)에서 발생하는 vanishing gradient problem을 해결하고, gate 입력에서 이전 hidden state를 제거하여 GRU보다 속도를 향상시킨 모델이며, Self-matching Network는 R-Net 모델에서 사용된 것으로, 자기 자신의 RNN sequence에 대하여 어텐션 가중치 (attention weight)를 계산하여 비슷한 의미 문맥 정보를 볼 수 있기 때문에 상호참조해결과 유사한 효과를 볼 수 있다. 본 논문에서는 한국어 기계 독해 데이터 셋을 구축하고, 여러 층의 SRU를 이용한 Encoder에 Self-matching layer를 추가한 $S^2$-Net 모델을 제안한다. 실험 결과, 본 논문에서 제안한 $S^2$-Net 모델이 한국어 기계 독해 데이터 셋에서 EM 65.84%, F1 78.98%의 성능을 보였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.11a
• /
• pp.82-82
• /
• 2008

One-dimensional (1D) nanowires have been received much attention due to their potential for applications in various field. Recently some logic applications fabricated on various nanowires, such as ZnO, CdS, Si, are reported. These logic circuits, which consist of two- or three field effect transistors(FETs), are basic components of computation machine such as central process unit (CPU). FETs fabricated on nanowire generally have surrounded shapes of gate structure, which improve the device performance. Highly integrated circuits can also be achieved by fabricating on nano-scaled nanowires. But the numerical and SPICE simulation about the logic circuitry have never been reported and analyses of detailed parameters related to performance, such as channel doping, gate shapes, souce/drain contact and etc., were strongly needed. In our study, NAND and NOT logic circuits were simulated and characterized using 2- and 3-dimensional numerical simulation (SILVACO ATLAS) and built-in spice module(mixed mode).

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.02a
• /
• pp.561-561
• /
• 2012

Graphene, two dimensional single layer of carbon atoms, has tremendous attention due to its superior property such as fast electron mobility, high thermal conductivity and optical transparency, and also found many applications such as field-effect transistors (FET), energy storage and conversion, optoelectronic device, electromechanical resonators and chemical sensors. Several techniques have been developed to form the graphene. Especially chemical vapor deposition (CVD) is a promising process for the large area graphene. For the electrically isolated devices, the graphene should be transfer to insulated substrate from Cu or Ni. However, transferred graphene has serious drawback due to remaining polymeric residue during transfer process which induces the poor device characteristics by impurity scattering and it interrupts the surface functionalization for the sensor application. In this study, we demonstrate the characteristics of solution-gated FET depending on the removal of polymeric residues. The solution-gated FET is operated by the modulation of the channel conductance by applying a gate potential from a reference electrode via the electrolyte, and it can be used as a chemical sensor. The removal process was achieved by several solvents during the transfer of CVD graphene from a copper foil to a substrate and additional annealing process with H2/Ar environments was carried out. We compare the properties of graphene by Raman spectroscopy, atomic force microscopy(AFM), and X-ray Photoelectron Spectroscopy (XPS) measurements. Effects of residual polymeric materials on the device performance of graphene FET will be discussed in detail.

• Nuclear Engineering and Technology
• /
• v.49 no.8
• /
• pp.1589-1599
• /
• 2017

Field programmable gate arrays (FPGAs) are getting more attention in safety-related and safety-critical application development of nuclear power plant instrumentation and control systems. The high logic density and advancements in architectural features make static random access memory (SRAM)-based FPGAs suitable for complex design implementations. Devices deployed in the nuclear environment face radiation particle strike that causes transient and permanent failures. The major reasons for failures are total ionization dose effects, displacement damage dose effects, and single event effects. Different from the case of space applications, soft errors are the major concern in terrestrial applications. In this article, a review of radiation effects on FPGAs is presented, especially soft errors in SRAM-based FPGAs. Single event upset (SEU) shows a high probability of error in the dependable application development in FPGAs. This survey covers the main sources of radiation and its effects on FPGAs, with emphasis on SEUs as well as on the measurement of radiation upset sensitivity and irradiation experimental results at various facilities. This article also presents a comparison between the major SEU mitigation techniques in the configuration memory and user logics of SRAM-based FPGAs.