• 전자통신동향분석
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• 제35권2호
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• pp.79-88
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• 2020

Quantum computing is regarded as one of the revolutionary computing technologies, and has attracted considerable attention in various fields, such as finance, chemistry, and medicine. One of the promising candidates to realize fault tolerant quantum computing is quantum dot qubits, due to their expectation of high scalability. In this study, we briefly introduce the international tendencies for quantum dot quantum computing. First, the current status of quantum dot gate operations is summarized. In most systems, over 99% of single qubit gate operation is realized, and controlled-not and controlled-phase gates as 2-qubit entangling gates are demonstrated in quantum dots. Second, several approaches to expand the number of qubits are introduced, such as 1D and 2D arrays and long-range interaction. Finally, the current quantum dot systems are evaluated for conducting quantum computing in terms of their number of qubits and gate accuracies. Quantum dot quantum computing is expected to implement scalable quantum computing. In the noisy intermediate-scale quantum era, quantum computing will expand its applications, enabling upcoming questions such as a fault-tolerant quantum computing architecture and error correction scheme to be addressed.

• 한국전기전자재료학회논문지
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• 제24권9호
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• pp.693-696
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• 2011

Recently, amorphous oxide semiconductors (AOSs) based thin-film transistors (TFTs) have received considerable attention for application in the next generation displays industry. The research trends of AOSs based TFTs investigation have focused on the high device performance. The electrical properties of the TFTs are influenced by trap density. In particular, the threshold voltage ($V_{th}$) and subthreshold swing (SS) essentially depend on the semiconductor/gate-insulator interface trap. In this article, we investigated the effects of Ar plasma-treated $SiO_2$ insulator on the interfacial property and the device performances of amorphous indium gallium zinc oxide (a-IGZO) TFTs. We report on the improvement in interfacial characteristics between a-IGZO channel layer and gate insulator depending on Ar power in plasma process, since the change of treatment power could result in different plasma damage on the interface.

• Journal of information and communication convergence engineering
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• 제15권3호
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• pp.151-159
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• 2017

Steganography, which is popular as an image processing technology, is the art of using digital images to hide a secret message in such a way that its existence can only be discovered by the sender and the intended receiver. This technique has the advantage of concealing secret information in a cover medium without drawing attention to it, unlike cryptography, which tries to convert data into something messy or meaningless. In this paper, we propose two efficient least significant bit (LSB)-based steganography techniques for designing an image-based steganography system on chip using hardware description language (HDL). The proposed techniques manipulate the LSB plane of the cover image to embed text inside it. The output of these algorithms is a stego-image which has the same quality as that of the original image. We also implement the proposed techniques using the Altera field programmable gate array (FPGA) and Quartus II design software.

• 한국전기전자재료학회논문지
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• 제25권3호
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• pp.187-192
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• 2012

Development of new efficient, high voltage switching devices with wide safe operating area and low on-state losses has received considerable attention in recent years. One of those structures with a very effective geometrical design is the trench gate Insulated Gate Bipolar Transistor(IGBT).power IGBT devices are optimized for high-voltage low-power design, decided to aim. Class 1,200 V NPT Planer IGBT, 1,200 V NPT Trench IGBT for class has been studied.

• 한국정보과학회 언어공학연구회:학술대회논문집(한글 및 한국어 정보처리)
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• 한국정보과학회언어공학연구회 2018년도 제30회 한글 및 한국어 정보처리 학술대회
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• pp.281-284
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• 2018

본 논문에서는 machine reading 분야에서 기존의 long short-term memory (LSTM) 모델이 가지는 문제점을 해결하는 새로운 네트워크를 제안하고자 한다. 기존의 LSTM 모델은 크게 두가지 제한점을 가지는데, 그 중 첫째는 forget gate로 인해 잊혀진 중요한 문맥 정보들이 복원될 수 있는 방법이 없다는 것이다. 자연어에서 과거의 문맥 정보에 따라 현재의 단어의 의미가 크게 좌지우지될 수 있으므로 올바른 문장의 이해를 위해 필요한 과거 문맥의 정보 유지는 필수적이다. 또 다른 문제는 자연어는 그 자체로 단어들 간의 복잡한 구조를 통해 문장이 이루어지는 반면 기존의 시계열 모델들은 단어들 간의 관계를 추론할 수 있는 직접적인 방법을 가지고 있지 않다는 것이다. 본 논문에서는 최근 딥 러닝 분야에서 널리 쓰이는 attention mechanism과 본 논문이 제안하는 restore gate를 결합한 네트워크를 통해 상기 문제를 해결하고자 한다. 본 논문의 실험에서는 기존의 다른 시계열 모델들과 비교를 통해 제안한 모델의 우수성을 확인하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.119-122
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• 2008

In this paper, we describe the current status and issues of the oxide thin-film transistors (OTFTs), which attract much attention as an emerging new backplane technology replacing conventional silicon-based TFTs technologies. First, the unique benefits of OTFTs will be presented as a backplane for large-sized AMOLED including note-book PC, second TV and HD-TV. And then, the state-of-the-art transistor performance and uniformity characteristics of OTFTs will be highlighted. The obtained a-IGZO TFTs exhibited the field-effect mobility of $18\;cm^2/Vs$, threshold voltage of 1.8 V, on/off ratio of $10^9$, and subthreshold gate swing of 0.28 V/decade. In addition, the world largest-sized 12.1-inch WXGA active-matrix organic light emitting diode (AMOLED) display is demonstrated using indium-gallium-zinc oxide (IGZO) TFTs.

• 한국전기전자재료학회논문지
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• 제26권2호
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• pp.87-91
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• 2013

Carbon-nanotube field-effect transistors (CNFETs) have drawn wide attention as one of the potential substitutes for metal-oxide-semiconductor field-effect transistors (MOSFETs) in the sub-10-nm era. Output characteristics of coaxially gated CNFETs were simulated using FETToy simulator to reveal the dependence of drain current on the nanotube diameter and gate oxide thickness. Nanotube diameter and gate oxide thickness employed in the simulation were 1.5, 3, and 6 nm. Simulation results show that drain current becomes large as the diameter of nanotube increases or insulator thickness decreases, and nanotube diameter affects the drain current more than the insulator thickness. An equation relating drain saturation current with nanotube diameter and insulator thickness is also proposed.

• EDISON SW 활용 경진대회 논문집
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• 제5회(2016년)
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• pp.295-298
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• 2016

Future logic device over the FinFET generation requires a complete electrostatics and transport characteristic for low-power and high-speed operation as extremely scaled devices. Silicon, Germanium and III-V based nanowire-based MOSFET devices and few-layer TMDC (Transition metal dichalcogenide monolayers) based multi-gate devices have been brought attention from device engineers due to those excellent electrostatic and novel device characteristic. In this study, we simulated ultrascaled Si/Ge/InAs gate-all-around nanowire MOSFET and MoS2 TMDC based DG MOSFET and TFET device by tight-binding NEGF method. As a result, we can find promising candidates of the future logic device of each channel material and device structures.

• 한국콘텐츠학회:학술대회논문집
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• 한국콘텐츠학회 2016년도 춘계 종합학술대회 논문집
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• pp.433-434
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• 2016

Cerebellar atrophy was found that a patient was taking oral phenytoin for 3 years. 53 years old female patient with General tonic clonic(GTC) type seizure was prescribed phenytoin. In the process, she developed ataxic gate, dysarthria. Brain magnetic resonance imaging(MRI) finding was revealed differential diagnosis cerebellar atrophy. She was prescribed epileptol instead of phenytoin. But leukopenia, thrombocytopenia occurred. As a result, phenytoin restarted. Development of medical state decreased abuse of anticonvulsants. Considering various convulsive disorders, we must give attention to using anticonvulsants.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.20-20
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• 2007

Nanowire-based field-effect transistors (FETs) decorated with nanoparticles have been greatly paid attention as nonvolatile memory devices of next generation due to their excellent transportation ability of charge carriers in the channel and outstanding capability of charge trapping in the floating gate. In this work, top-gate single ZnO nanowire-based FETs with and without Au nanoparticles were fabricated and their memory effects were characterized. Using thermal evaporation and rapid thermal annealing processes, Au nanoparticles were formed on an $Al_2O_3$ layer which was semi cylindrically coated on a single ZnO nanowire. The family of $I_{DS}-V_{GS}$ curves for the double sweep of the gate voltage at $V_{DS}$ = 1 V was obtained. The device decorated with nanoparticles shows giant hysterisis loops with ${\Delta}V_{th}$ = 2 V, indicating a significant charge storage effect. Note that the hysterisis loops are clockwise which result from the tunneling of the charge carriers from the nanowire into the nanoparticles. On the other hand, the device without nanoparticles shows a negligible countclockwise hysterisis loop which reveals that the influence of oxide trap charges or mobile ions is negligible. Therefore, the charge storage effect mainly comes from the nanoparticles decorated on the nanowire, which obviously demonstrates that the top-gate single ZnO nanowire-based FETs decorated with Au nanoparticles are the good candidate for the application in the nonvolatile memory devices of next generation.