• The Journal of the Acoustical Society of Korea
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• v.39 no.5
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• pp.483-489
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• 2020

This paper proposes acoustic model training using self-attention for low-resource speech recognition. In low-resource speech recognition, it is difficult for acoustic model to distinguish certain phones. For example, plosive /d/ and /t/, plosive /g/ and /k/ and affricate /z/ and /ch/. In acoustic model training, the self-attention generates attention weights from the deep neural network model. In this study, these weights handle the similar pronunciation error for low-resource speech recognition. When the proposed method was applied to Time Delay Neural Network-Output gate Projected Gated Recurrent Unit (TNDD-OPGRU)-based acoustic model, the proposed model showed a 5.98 % word error rate. It shows absolute improvement of 0.74 % compared with TDNN-OPGRU model.

• Journal of IKEEE
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• v.25 no.3
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• pp.473-478
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• 2021

Although CNTFETs have attracted great attention due to their ability to increase semiconductor device performance by about 13 times, the commercialization of CNTFETs has been challenging because of the immature deposition process of CNTs. To overcome these difficulties, circuit design method considering the known limitations of the CNTFET manufacturing process is receiving increasing attention. SRAM is a major element constituting microprocessor and is regularly and repeatedly positioned in the cache memory; so, it has the advantage that CNTs can be more easily and densely deposited in SRAM than other circuit blocks. In order to take these advantages, this paper presents a circuit design method for SRAM cells considering CNT density and then evaluates its performance improvement using HSPICE simulation. As a result of simulation, it is found that when CNTFET is applied to SRAM, the gate width can be reduced by about 1.7 times and the read speed also can be improved by about 2 times when the CNT density was increased in the same gate width.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.4
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• pp.376-382
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• 2014

This paper proposes the pulse width modulation (PWM) control strategy for low-speed operation in the three-level neutral-point-clamped (NPC) inverters based on the bootstrap gate drive circuit. As a purpose of the cost reduction, several papers have paid attention to the bootstrap circuit applied to the three-level NPC inverter. However, the bootstrap gate driver IC cannot generate the gate signal to the IGBT for low-speed operation, because the bootstrap capacitor voltage decreases under the threshold level. For low-speed operation, the dipolar and partial-dipolar modulations can be the effective solution. However, these modulations have drawbacks in terms of the switching loss and THD. Therefore, this paper proposes the PWM control strategy to operate the inverter at low-speed and to minimize the switching loss and harmonics. The experimental results are presented to verify the validity on the proposed method.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.7 no.10
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• pp.895-903
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• 2017

Quantum Cellular Automata(QCA) is one of the proposed techniques as an alternative solution to the fundamental limitations of CMOS. QCA has recently been extensively studied along with experimental results, and is attracting attention as a nano-scale size and low power consumption. Although the XOR gates proposed in the previous paper can be designed using the minimum area and the number of cells, there is a disadvantage that the number of added cells is increased due to the stability and the accuracy of the result. In this paper, we propose a gate that supplement for the drawbacks of existing XOR gates. The XOR gate of this paper reduces the number of cells by arranging AND gate and OR gate with square structure and propose a half-adder by adding two cells that serve as simple inverters using the proposed XOR gate. Also This paper use QCADesginer for input and result accuracy. Therefore, the proposed half-adder is composed of fewer cells and total area compared to the conventional half-adder, which is effective when used in a large circuit or when a half - adder is needed in a small area.

• Proceedings of the KSME Conference
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• 2003.11a
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• pp.1932-1938
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• 2003

We have applied spectroscopic ellipsometry to investigate $high-{\kappa}$ dielectric thin films and correlate their optical properties with fabrication processes, in particular, with high temperature annealing. The use of high-k dielectrics such as $HfO_{2}$, $Ta_{2}O_{5}$, $TiO_{2}$, and $ZrO_{2}$ as the replacement for $SiO_{2}$ as the gate dielectric in CMOS devices has received much attention recently due to its high dielectric constant. From the characteristics found in the pseudo-dielectric functions or the Tauc-Lorentz dispersions, the optical properties such as optical band gap, polycrystallization, and optical density will be discussed.

• The Journal of the Korea Contents Association
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• v.17 no.3
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• pp.474-485
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• 2017

Sungnyemun Gate, Korea's National Treasure No.1, was destroyed by fire on February 10, 2008 and has been re-opened to the public again as of May 4, 2013 after a reconstruction work. Sungnyemun Gate become a national issue and draw public attention to be a major topic on news or research. In this research, text mining and association rule mining techniques were used on keyword of newspaper articles related to Sungnyemun Gate as a cultural heritage from 2002 to 2016 to find major keywords and keyword association rule. Next, we analyzed some typical and specific keywords that appear frequently and partially depending on before and after the fire and newpaper companies. Through this research, the trends and keywords of newspapers articles related to Sungnyemun Gate could be understood, and this research can be used as fundamental data about Sungnyemun Gate to information producer and consumer.

• Journal of the Korean Society of Safety
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• v.3 no.2
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• pp.5-16
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• 1988

This study is conducted to evaluate the explosion of tolune storage tank in the petrochemical plant by Fault Tree Analysis. The conclusions are as follows; 1) Fault Tree diagram and the required computer program for evaluation of explosion accident is developed. 2) The probability of the top event, explosion accident, is $1.5\;{\times}\;10^{-8}$ per year, so there is almost no possibility of explosion during the life cycle of tank. However, the probability of Gate 6 and Gate 7 is 8.8 per month, therefore, attention should be paid to them for accident prevention. 3) The number of minimal cut sets is 67 sets which are not calculated the probability of each set, because of the lack of computer capacity. All the minimal cut sets should be examined case by case. However, it is necessary to be paid attention to COM1, 126, 131, and COM4 in minimal cut sets, because the number of appearance is so high. 4) The number path sets is 70 sets which are not calculated the probability of each set, because of the lack of computer capacity. It is very useful to prepare safety checklist by using this minimal path sets. Also, the events which appear many times, 123, COM5, 139, 127 and 128, are very high in reliability.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1297-1298
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• 2006

Omega-shaped-gate (OSG) nanowire-based field effect transistors (FETs) have been attracted recently attention due to their highdevice performance expected from theoretical simulations among nanowire-based FETs with other gate geometries. OSG FETs with the channels of ZnO nanowires were successfully fabricated in this study with photolithographic processes. In the OSG FETs fabricated on oxidized Si substrates, the channels of ZnO nanowires with diameters of about 60 nm are coated surroundingly by $Al_{2}O_{3}$ as gate dielectrics with atomic layer deposition. About 80 % of the surfaces of the nanowires coated with $Al_{2}O_{3}$ is covered with gate metal to form OSG FETs. A representative OSG FET fabricated in this study exhibits a mobility of 98.9 $cm^{2}/Vs$, a peak transconductance of 0.4 ${\mu}S$, and an Ion/Ioff ratio of $10^6$ the value of the Ion/Ioff ratio obtained from this OSG FET is the highest among nanowire-based FETs, to our knowledge. Its mobility, peak transconductance, and Ion/Ioff ratio arc remarkably enhanced by 11.5, 32, and $10^6$ times, respectively, compared with a back-gate FET with the same ZnO nanowire channel as utilized in the OSG FET.

• Proceedings of the Korea Information Processing Society Conference
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• 2022.11a
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• pp.300-302
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• 2022

Palm vein identification has attracted attention due to its distinct characteristics and excellent recognition accuracy. However, many contactless palm vein identification systems suffer from the issue of having low-quality palm images, resulting in degradation of recognition accuracy. This paper proposes the use of U-Net architecture to correctly segment the vascular blood vessel from palm images. Attention gate mechanism and residual block are also utilized to effectively learn the crucial features of a specific segmentation task. The experiments were conducted on CASIA dataset. Hessian-based Jerman filtering method is applied to label the palm vein patterns from the original images, then the network is trained to segment the palm vein features from the background noise. The proposed method has obtained 96.24 IoU coefficient and 98.09 dice coefficient.

• Journal of IKEEE
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• v.13 no.2
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• pp.126-131
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• 2009

To overcome short channel effects, wrap-around field effect transistors have drawn a great deal of attention for their superior electrostatic coupling between the channel and the surrounding gate electrode. In this paper, we introduce a bottom-up technique to fabricate a wrap-around field effect transistor using silicon nanowires as the conduction channel. Device fabrication was consisted mainly of electron-beam lithography, dielectrophoresis to accurately align the nanowires, and the formation of gate electrode using electrochemical deposition. The electrolyte for electrochemical deposition was made up of non-toxic organic-based solution and liquid nitrogen was used as a method of maintaining the shape of polymethyl methacrylate(PMMA) during the process of electrochemical deposition. Patterned PMMA can be used as a nano-template to produce wrap-around gate nano-structures.