• 한국표면공학회:학술대회논문집
• /
• 한국표면공학회 2014년도 추계학술대회 논문집
• /
• pp.15-15
• /
• 2014

Block Copolymer(BCP) 는 self assembly 현상을 이용하여 다양한 pattern을 형성하는데 용이한 물질로써 이를 이용한 다양한 구조물 제작에 대한 연구가 활발히 진행되고 있다. 본 연구에서는 hoe pattern 모양을 갖는 BCP 패턴을 이용하여 Atomic Layer Deposition(ALD) 및 Reactive Ion Etching(RIE) 공정을 이용한 3차원 quantum tube 구조물을 제작하였다.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
• /
• pp.19-27
• /
• 2003

Morphology and composition of MgO films grown on single-crystalline diamond (100) have been studied. MgO thin films were deposited in the substrate temperature range from room temperature (RT) to 723K by means of electron beam evaporation using MgO powder source. Atomic force microscopy images indicated that the film grown at RT without $O_2$ supply was relatively uniform and flat whereas that deposited in oxygen ambient yielded higher growth rates and rough surface morphologies. X-ray photoelectron spectroscopy analyses demonstrate that the MgO film deposited at RT without $O_2$ has the closest composition to the stoichiometric MgO, and that a thin contaminant layer composed mainly of magnesium peroxide (before etching) or hydroxide (after etching) was unintentionally formed on the film surface, respectively. These results will be discussed in relation to the interaction among the evaporated species and intentionally supplied oxygen molecules at the growth front as well as the interfacial energy between diamond and MgO.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
• /
• pp.83-83
• /
• 2008

Metal-oxide-silicon-on-insulator (MOSOI) structures were fabricated to study the effect caused by reactive ion etching (RIE) and sacrificial oxidation process on silicon-on-insulator (SOI) layer. The MOSOI capacitors with an etch-damaged SOI layer were characterized by capacitance-voltage (C-V) measurements and compared to the sacrificial oxidation treated samples and the reference samples without etching treatment. The measured C-V curves were compared to the numerical results from 2-dimensional (2-D) simulations. The measurements revealed that the profile of C-V curves significantly changes depending on the SOI surface condition of the MOSOI capacitors. The shift in the measured C-V curves, due to the difference of the fixed oxide charge ($Q_f$), together with the numerical simulation analysis and atomic force microscopy (AFM) analysis, allowed extracting the fixed oxide charges ($Q_f$) in the structures as well as 2-D carrier distribution profiles.

• Transactions on Electrical and Electronic Materials
• /
• 제11권4호
• /
• pp.190-193
• /
• 2010

This report covers an effective fabrication method of graphene nanoribbon for top-gated field effect transistors (FETs) utilizing electron beam lithography with a bi-layer resists (XR-1541/poly methtyl methacrylate) process. To improve the variation of the gating properties of FETs, the residues of an e beam resist on the graphene channel are successfully taken off through the combination of reactive ion etching and a lift-off process for the XR-1541 bi-layer. In order to identify the presence of graphene structures, atomic force microscopy measurement and Raman spectrum analysis are performed. We believe that the lift-off process with bi-layer resists could be a good solution to increase gate dielectric properties toward the high quality of graphene FETs.

• 한국진공학회지
• /
• 제13권3호
• /
• pp.120-126
• /
• 2004

트렌치 소자 제조시 게이트 산화막 성장과 내압 강하의 원인이 되는 식각손상 회복과 코너 영역의 구조를 개선하기 위해 수소 분위기 열처리를 하였다. 열처리시 수소 원자에 의한 환원 반응을 이용하여 표면 에너지가 높은 코너 영역에서는 원자들의 이동에 의한 결정면 재배열, 산화막 측벽에서의 실리콘 원자 적층, 표면 거칠기의 개선 효과 등을 전자현미경 관찰을 통해 확인하였다. 실리콘 원자의 이동을 방해하는 식각 후 잔류 산화막을 수소 가스의 환원성 분위기에서 열처리함으로써 표면 에너지를 낮추는 방향으로 원자의 이동이 일어나 concave 영역, 즉 트렌치 bottom corner에서는 (111), (311) 결정면 재분포 현상이 일어남을 확인할 수 있었다. 또한 convex comer에서의 원자 이동으로 인해 corner 영역에서는 (1111) 면의 step 들이 존재하게 되고 원자 이동에 의해 산화막 측벽에 이르러 이동된 원자의 적층이 일어나며, 이는 열처리시 표면 손상 회복이 원자이동에 의함을 나타낸다. 이러한 적층은 표면 상태가 깨끗할수록 정합성을 띄어 기판과 일치하는 에피 특성을 나타내고 열처리 온도가 높을수록 표면 세정 효과가 커져 식각손상 회복효과가 커지며, 이를 이용하여 이후의 산화막 성장시 균일한 두께를 코너영역에서 얻을 수 있었다

• 한국진공학회지
• /
• 제20권1호
• /
• pp.63-69
• /
• 2011

본 연구에서는 기존 실리콘 반도체 기술 기반의 포토 및 이빔 리소그래피 공정을 통하여 유기 반도체 소자를 패터닝하였다. P3HT나 PEDOT 등의 유기 반도체는 용매에 녹기 때문에 MIMIC (micro-molding in capillaries)이나 inkjet printing 기술을 이용하여 마이크로미터 크기의 소자 제작이 가능하였으나, 펜타신은 용매에 녹지 않기 때문에 매우 복잡한 방법으로 마이크로미터 크기의 소자를 제작하여왔다. 그러나, 본 연구에서는 원자층 증착 방법으로 증착한 산화 알루미늄막을 펜타신의 보호층으로 이용하여 기존의 포토 및 이빔 리소그래피 방법으로 마이크로미터크기의 펜타신 소자를 제작하였으며 그 전기 특성을 확인하였다.

• 한국재료학회지
• /
• 제29권11호
• /
• pp.697-702
• /
• 2019

In this study, using a wet chemical process, we evaluate the effectiveness of different solution concentrations in removing layers from a solar cell, which is necessary for recovery of high-purity silicon. A 4-step wet etching process is applied to a 6-inch back surface field(BSF) solar cell. The metal electrode is removed in the first and second steps of the process, and the anti-reflection coating(ARC) is removed in the third step. In the fourth step, high purity silicon is recovered by simultaneously removing the emitter and the BSF layer from the solar cell. It is confirmed by inductively coupled plasma mass spectroscopy(ICP-MS) and secondary ion mass spectroscopy(SIMS) analyses that the effectiveness of layer removal increases with increasing chemical concentrations. The purity of silicon recovered through the process, using the optimal concentration for each process, is analyzed using inductively coupled plasma atomic emission spectroscopy(ICP-AES). In addition, the silicon wafer is recovered through optimum etching conditions for silicon recovery, and the solar cell is remanufactured using this recovered silicon wafer. The efficiency of the remanufactured solar cell is very similar to that of a commercial wafer-based solar cell, and sufficient for use in the PV industry.

• 한국재료학회:학술대회논문집
• /
• 한국재료학회 2011년도 춘계학술발표대회
• /
• pp.26.1-26.1
• /
• 2011

We investigated the atomic layer deposition (ALD) process for nitrogen doped ZnO and the application for n-ZnO : N/p-Si (NW) coaxial hetero-junction photodetectors. ALD ZnO:N was deposited using diethylzinc (DEZ) and diluted $NH_4OH$ at $150^{\circ}C$ of substrate temperature. About 100~300 nm diameter and 5 um length of Si nanowires array were prepared using electroless etching technique in 0.108 g of $AgNO_3$ melted 20 ml HF liquid at $75^{\circ}C$. TEM images showed ZnO were deposited on densely packed SiNW structure achieving extraordinary conformality. When UV (360 nm) light was illuminated on n-ZnO:N/p-SiNW, I-V curve showed about three times larger photocurrent generation than film structure at 10 V reverse bias. Especially, at 660 nm wave length, the coaxial structure has 90.8% of external quantum efficiency (EQE) and 0.573 A/W of responsivity.

• 한국윤활학회:학술대회논문집
• /
• 한국윤활학회 2002년도 제35회 춘계학술대회
• /
• pp.40-44
• /
• 2002

The motivation of this work is to use SAM(Self-Assembled Monolayer) for developing a rapid and flexible non-photolithographic nano-structure fabrication technique which can be utilized in micro-machining of metals as well as silicon-based materials. The fabrication technique implemented in this work consists of a two-step process, namely, mechanical scribing followed by chemical etching. From the experimental results, it was found that thiol on copper surface could be removed even under a few nN normal load. The nano-tribological characteristics of thiol-SAM on various metals were largely dependent on the native oxide layer of metals. Based on these findings, nano-patterns with sub-micrometer width and depth on metal surfaces such as Cu, Au and Ag could be obtained using a diamond-coated tip.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2009년도 제38회 동계학술대회 초록집
• /
• pp.84-84
• /
• 2010

In this study, we report on the novel lithographic patterning method to fabricate organic-semiconductor devices based on photo and e-beam lithography with well-known silicon technology. The method is applied to fabricate pentacene-based organic field effect transistors. Owing to their solubility, sub-micron sized patterning of P3HT and PEDOT has been well established via micromolding in capillaries (MIMIC) and inkjet printing techniques. Since the thermally deposited pentacene cannot be dissolved in solvents, other approach was done to fabricate pentacene FETs with a very short channel length (~30nm), or in-plane orientation of pentacene molecules by using nanometer-scale periodic groove patterns as an alignment layer for high-performance pentacene devices. Here, we introduce the atomic layer deposition of $Al_2O_3$ film on pentacene as a passivation layer. $Al_2O_3$ passivation layer on OTFTs has some advantages in preventing the penetration of water and oxygen and obtaining the long-term stability of electrical properties. AZ5214 and ma N-2402 were used as a photo and e-beam resist, respectively. A few micrometer sized lithography patterns were transferred by wet and dry etching processes. Finally, we fabricated sub-micron sized pentacene FETs and measured their electrical characteristics.