• The Transactions of the Korean Institute of Electrical Engineers
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• v.33 no.2
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• pp.47-55
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• 1984

This paper is concerned with a computer-aided state assignment, that is, coding race-free internal states of asynchronous sequential circuits, and a method for minimizing the combinational network of asynchronous sequential circuits. The FORTRAN version of the peoposed algorithm results in race-free state assignments and reduction of the number of connections and gates with near minimal hardware cost. Some examples are designed by the proposed computer program to illustrate the algorithm in this paper. Finally, results are compared with those of the other methods.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.9
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• pp.38-48
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• 1998

Generating test patterns for asynchronous sequential circuits remains to be a very difficult problem. There are few algorithms for this problem, and previous works cut feedback loops, and insert synchronous flip-flops in the feedback loops during ATPG. The conventional algorithms are similar to the algorithms for synchronous sequential circuits. This means that the conventional algorithms generate test patterns by modeling asynchronous sequential circuits as synchronous sequential circuits. So, test patterns generated by those algorithms nay not detect target faults when the test patterns are applied to the asynchronous sequential circuit under test. In this paper an algorithm is presented to generate test patterns for asynchronous sequential circuits. Test patterns generated by the algorithm can detect target faults for asynchronous sequential circuits with the minimal possibility of critical race problem and oscillation. And it is guaranteed that the test patterns generated by the algorithm will detect target faults.

• Journal of Institute of Control, Robotics and Systems
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• v.17 no.11
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• pp.1125-1131
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• 2011

This paper presents a control theoretic approach to realizing fault tolerance in asynchronous sequential circuits. The considered asynchronous circuit is assumed to work in space environment and is subject to faults caused by total ionizing dose (TID) effects. In our setting, TID effects cause permanent changes in state transition characteristics of the asynchronous circuit. Under a certain condition of reachability redundancy, it is possible to design a corrective controller so that the closed-loop system can maintain the normal behavior despite occurrences of TID faults. As a case study, the proposed control scheme is applied to an asynchronous arbiter implemented in FPGA.

• Journal of the Korean Institute of Telematics and Electronics
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• v.11 no.2
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• pp.22-26
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• 1974

To synthesize transition-sensitive asynchronous sequential circuits, D-type transition-sensitive flip-flop is used.4 new concept, a pair of input state is introduced and used to reduce the number of internal states. We proposed an algorithm to synthesize multiple-input change asynchronous sequential circuits directly from a primitive state table an6 demonstrated the method is better than the one which is due to Bredeson and Hulina and Others.

• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.3
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• pp.399-408
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• 2022

This paper proposes a corrective control system to achieve fault-tolerant control for input/output asynchronous sequential circuits vulnerable to transient faults violating fundamental mode operations. To overcome non-fundamental mode faults occurring in transient transitions of asynchronous sequential circuits, it is necessary to determine the end of unauthorized state transitions caused by the faults and to stably take the circuit from the faulty state to a desired state that is output equivalent with the normal next stable state. We address the existence condition for a proper output-feedback corrective controller that achieves fault diagnosis and fault-tolerant control for these non-fundamental mode faults. The corrective controller and asynchronous sequential circuit are implemented on field-programming gate array to demonstrate the synthesis procedure and applicability of the proposed control scheme.

• Journal of the Korean Institute of Intelligent Systems
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• v.26 no.2
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• pp.135-140
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• 2016

Corrective controllers enable fault diagnosis and tolerance for various faults in asynchronous sequential circuits without resort to redesign. In this paper, we propose a static corrective controller in order to decrease the size of the controller. Compared with dynamic controllers, static controllers can be made using only combinational circuits, as they need no inner states. We address the existence condition and design procedures for static corrective controllers that overcome state transition faults. To show the validity and advantage, the proposed controller is applied to an SEU error counter implemented on FPGA.

• Journal of the Korea Society for Simulation
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• v.10 no.1
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• pp.25-34
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• 2001

In this paper, we describe the generation method of interface logic which replace between IP & IP handshaking signal with asynchronous logic circuit. Especially, we suggest the new asynchronous sequential "Waveform to VHDL" code creation algorithm by flow chart conversion : Wave2VHDL - if only mixed asynchronous timing waveform is presented the level type input and pulse type input for handshaking, we convert waveform to flowchart and then replace with VHDL code according to converted flowchart. Also, we confirmed that asynchronous electronic circuits are created by applying extracted VHDL source code from suggest algorithm to conventional domestic/abroad CAD Tool, Finally, we assured the simulation result and the suggest timing diagram are identical.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.32 no.11
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• pp.404-416
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• 1983

This paper is concerned with the design automation of the sequential machines. The operations of sequential machine can be diveded into two types such as synchronous and asynchronous sequential machine and their realization is treated in separate mode. But, in order to integrate logic circuits in high volume, mixed mode sequential machine uses common circuitry that consists of gates and flip-flops. Proposed sequential machine can be designed by several method, which are hard-wired implementation, firmware realization by PLA and ROM. And then onr example shows the differnces among three design mothods. Finally, computer algorithm(called MINIPLA) is discussed for various application of mixed-mode sequential machine.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.4
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• pp.39-48
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• 2009

Asynchronous sequential machines, or clockless logic circuits, have several advantages over synchronous machines such as fast operation speed, low power consumption, etc. In this paper, we propose a novel robust controller for input/output asynchronous sequential machines with uncertain state transitions. Due to model uncertainties or inner failures, the state transition function of the considered asynchronous machine is not completely known. In this study, we present a formulation to model this kind of asynchronous machines ana using generalized reachability matrices, we address the condition for the existence of an appropriate controller such that the closed-loop behavior matches that of a prescribed model. Based on the previous research results, we sketch design procedure of the proposed controller and analyze the stable-state operation of the closed-loop system.

• Journal of the Korean Institute of Telematics and Electronics
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• v.12 no.2
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• pp.24-27
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• 1975

A Synthesis method for multiple-input change transition-sensitive asynchronous sequential circuits is proposed. Both internal states and output states are synthesized from primitive flow tables. It is Btown that cur realization is faster than that of Chuang's. It is pointed out that Chuang's realization of output states contains malfunctions. In this paper, output stales are easily realized from primitive flaw table by the method of controlled excitation.