• 제목/요약/키워드: Array chip

검색결과 531건 처리시간 0.03초

BGA to CSP to Flip Chip-Manufacturing Issues

  • Caswell, Greg;Partridge, Julian
    • 마이크로전자및패키징학회지
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    • 제8권2호
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    • pp.37-42
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    • 2001
  • The BGA package has been the area array package of choice for several years. Recently, the transition has been to finer pitch configurations called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch. requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and place equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

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BGA to CSP to Flip Chip - Manufacturing Issues

  • Caswell, Greg;Partridge, Julian
    • 한국마이크로전자및패키징학회:학술대회논문집
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    • 한국마이크로전자및패키징학회 2001년도 Proceedings of 6th International Joint Symposium on Microeletronics and Packaging
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    • pp.27-34
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    • 2001
  • The BGA Package has been the area array package of choice for several rears. Recently, the transition has been to finer pitch configuration called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch, requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and piece equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

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Four-channel GaAs multifunction chips with bottom RF interface for Ka-band SATCOM antennas

  • Jin-Cheol Jeong;Junhan Lim;Dong-Pil Chang
    • ETRI Journal
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    • 제46권2호
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    • pp.323-332
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    • 2024
  • Receiver and transmitter monolithic microwave integrated circuit (MMIC) multifunction chips (MFCs) for active phased-array antennas for Ka-band satellite communication (SATCOM) terminals have been designed and fabricated using a 0.15-㎛ GaAs pseudomorphic high-electron mobility transistor (pHEMT) process. The MFCs consist of four-channel radio frequency (RF) paths and a 4:1 combiner. Each channel provides several functions such as signal amplification, 6-bit phase shifting, and 5-bit attenuation with a 44-bit serial-to-parallel converter (SPC). RF pads are implemented on the bottom side of the chip to remove the parasitic inductance induced by wire bonding. The area of the fabricated chips is 5.2 mm × 4.2 mm. The receiver chip exhibits a gain of 18 dB and a noise figure of 2.0 dB over a frequency range from 17 GHz to 21 GHz with a low direct current (DC) power of 0.36 W. The transmitter chip provides a gain of 20 dB and a 1-dB gain compression point (P1dB) of 18.4 dBm over a frequency range from 28 GHz to 31 GHz with a low DC power of 0.85 W. The P1dB can be increased to 20.6 dBm at a higher bias of +4.5 V.

Multianalyte Sensor Array using Capillary-Based Sample Introduction Fluidic Structure: Toward the Development of an "Electronic Tongue"

  • 손영수
    • 센서학회지
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    • 제13권5호
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    • pp.378-382
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    • 2004
  • A micromachined fluidic structure for the introduction of liquid samples into a chip-based sensor array composed of individually addressable polymeric microbeads has been developed. The structure consists of a separately attached cover glass, a single silicon chip having micromachined channels and microbead storage cavities, and a glass carver. In our sensor array, transduction occurs via colorimetric and fluorescence changes to receptors and indicator molecules that are covalently attached to termination sites on the polymeric microbeads. Data streams are acquired for each of the individual microbeads using a CCD. One of the key parts of the structure is a passive fluid introduction system driven only by capillary force. The velocity of penetration of a horizontal capillary for the device having a rectangular cross section has been derived, and it is quite similar to the Washburn Equation calculated for a pipe with a circular cross section having uniform radius. The test results show that this system is useful in a ${\mu}$-TAS and biomedical applications.

Nano Pillar Array 사출성형을 이용한 DNA 분리 칩 개발 (Development of the DNA Sequencing Chip with Nano Pillar Array using Injection Molding)

  • 김성곤;최두선;유영은;제태진;김태훈;황경현
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 2005년도 춘계학술대회 논문집
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    • pp.1206-1209
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    • 2005
  • In recent, injection molding process for features in sub-micron scale is under active development as patterning nano-scale features, which can provide the master or stamp for molding, and becomes available around the world. Injection molding has been one of the most efficient processes for mass production of the plastic product, and this process is already applied to nano-technology products successfully such as optical storage media like DVD or BD which is a large area plastic thin substrate with nano-scale features on its surface. Bio chip for like DNA sequencing may be another application of this plastic substrate. The DNA can be sequenced using order of 100 nm pore structure when making the DNA flow through the pore structure. Agarose gel and silicon based chip have been used to sequence the DNA, but injection molded plastic chip may have benefit in terms of cost. This plastic DNA sequencing chip has plenty of pillars in order of 100 nm in diameter on the substrate. When the usual features in case of DVD or BD have very low aspect ratio, even less than 0.5, but the DNA chip will have relatively high aspect ratio of about 2. It is not easy to injection mold the large area thin substrate with sub-micron features on its surface due to the characteristics of the molding process and it becomes much more difficult when the aspect ratio of the features becomes high. We investigated the effect of the molding parameters for injection molding with high aspect ratio nano-scale features and injection molded some plastic DNA sequencing chips. We also fabricated PR masters and Ni stamps of the DNA chip to be used for molding

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Realizing TDNN for Word Recognition on a Wavefront Toroidal Mesh-array Neurocomputer

  • Hong Jeong;Jeong, Cha-Gyun;Kim, Myung-Won
    • Journal of Electrical Engineering and information Science
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    • 제1권1호
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    • pp.98-107
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    • 1996
  • In this paper, we propose a scheme that maps the time-delay neural network (TDNN) into the neurocomputer called EMIND-II which has the wavefront toroidal mesh-array structure. This neurocomputer is scalable, consists of many timeshared virtual neurons, is equipped with programmable on-chip learning, and is versatile for building many types of neural networks. Also we define the programming model of this array and derive the parallel algorithms about TDNN for the proposed neurocomputer EMIND-II. In addition, the computational complexities for the parallel and serial algorithms are compared. Finally, we introduce an application of this neurocomputer to word recognition.

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편파가변 위성 방송 수신용 능동 위상 배열 안테나 개발 (Development of Polarization-Controllable Active Phased Array Antenna for Receiving Satellite Broadcasting)

  • 최진영;이호선;공동욱;전종훈
    • 한국전자파학회논문지
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    • 제29권5호
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    • pp.325-335
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    • 2018
  • 본 논문에서는 이동체의 움직임 및 그에 따른 편파 도래각 변화에 대응 가능한 위성 수신용 능동 위상 배열 안테나를 개발하도록 한다. 이를 위하여 이중편파를 10.7~14.5 GHz의 Ku 대역에서 동시에 구현 가능한 비발디 안테나와 효과적으로 위상 및 이득을 제어할 수 있는 MFC(Multi-Function Core) 칩을 자체 개발하였으며, 이를 이용하여 수신 모듈과 제어 모듈로 이루어진 능동 위상 배열 안테나를 제작하였다. 제작 결과, $60^{\circ}$ 각도까지의 깨끗한 빔 조향 특성과 높은 격리도의 편파 가변 특성을 확인하였다.

N-GaN 접촉 전극의 크기 및 배열 변화에 따른 패드리스 수직형 발광다이오드의 구동전압의 변화에 관한 연구 (The Effects of Size and Array of N-GaN Contacts on Operation Voltage of Padless Vertical Light Emitting Diode)

  • 노호균;하준석
    • 마이크로전자및패키징학회지
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    • 제21권1호
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    • pp.19-23
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    • 2014
  • LED (Light Emitting Diode) 시장의 발전이 빠르게 이루어지고 있음에 따라 점차 고효율 LED의 필요성이 증가하고 있다. 이에 우리는 Hole Type의 Padless 신 구조 수직형 LED에서, 접촉 전극의 크기와 그 배치가 Chip의 가동 전압에 어떠한 영향을 미치는지 알아보았다. 이를 위하여 LED simulation을 통한 계산과 실제 Chip 제작을 통한 전기적 특성 평가를 하였다. 그 결과, Simulation 을 통하여 n전극의 크기가 커질수록 구동전압이 낮아짐을 확인하였고, N 전극의 형태가 확산됨에 따라서도 구동전압이 낮아짐을 확인하였다. 이러한 추세는 실제 제작한 LED Chip의 측정 결과와 비슷한 경향을 나타내었다.

Light-Adaptive Vision System for Remote Surveillance Using an Edge Detection Vision Chip

  • Choi, Kyung-Hwa;Jo, Sung-Hyun;Seo, Sang-Ho;Shin, Jang-Kyoo
    • 센서학회지
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    • 제20권3호
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    • pp.162-167
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    • 2011
  • In this paper, we propose a vision system using a field programmable gate array(FPGA) and a smart vision chip. The output of the vision chip is varied by illumination conditions. This chip is suitable as a surveillance system in a dynamic environment. However, because the output swing of a smart vision chip is too small to definitely confirm the warning signal with the FPGA, a modification was needed for a reliable signal. The proposed system is based on a transmission control protocol/internet protocol(TCP/IP) that enables monitoring from a remote place. The warning signal indicates that some objects are too near.

모아레 간섭계를 이용한 Flip Chip PBGA 패키지의 온도변화에 대한 거동해석 (Thermo-mechanical Analysis of Filp Chip PBGA Package Using $Moir\acute{e}$ Interferometry)

  • 김도형;최용서;주진원
    • 대한기계학회:학술대회논문집
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    • 대한기계학회 2003년도 추계학술대회
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    • pp.1027-1032
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    • 2003
  • Thermo-mechanical behavior of flip-chip plastic ball grid array (FC-PBGA) packages are characterized by high sensitive $Moir{\acute{e}}$ interferometry. $Moir{\acute{e}}$ fringe patterns are recorded and analyzed for several temperatures. Deformation analysis of bending displacements of the packages and average strains in the solder balls for a single-sided package assembly and a double-sided package assembly are presented. The bending displacement of the double-sided package assembly is smaller than that of the single-sided one. The largest of effective strain occurred in the solder ball located at the edge of the chip and its magnitude of the double-sided package assembly is greater than that of single-sided one.

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