• Journal of Institute of Control, Robotics and Systems
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• v.13 no.7
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• pp.649-655
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• 2007

In this paper, a time-delayed controller for position control of humanoid robot arms is designed and implemented on a field programmable gate array(FPGA) chip. The time-delayed control algorithm is simple to implement, and robust to reject disturbances. The time-delayed control method uses the one sample time-delayed previous information to cancel out uncertainties in the system. Since the sampling time is so fast with the current hardware technology, the time-delayed controller can be implemented. However, inertia values should be correctly estimated to have the better performance. The position tracking tasks of humanoid robot arms are tested to compare performances of several control algorithms including the time-delayed controller.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.4
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• pp.85-92
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• 1995

A new partitioning algorithm has been developed to implement a large circuit by using multiple field programmable gate array (FPGA) chips. While the conventional partitioning is to minimze the number of nets cut under size constraints, partitioning for multiple FPGAs has several additional constraints so that each partitioned subcircuit can be implemented in a FPGA chip. To obtain satisfactory results under the constraints, the partitioning is performed in two steps whhich are the intial partitioning for global optimization and the iterative partitioning improvements for constraint satisfaction. Experismental results using the MCNC benchmark examples show that our partition method produces better results thatn those of other recent approaches on the average.

• Journal of Korea Society of Digital Industry and Information Management
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• v.8 no.1
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• pp.117-123
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• 2012

This paper implements mobile Worldwide Interoperability for Microwave Access (WiMAX) receiver using Software Defined Radio (SDR) technology. SDR system is difficult to implement on the mobile handset because of restrictions that are computing power and under space constraints. The implemented receiver processes mobile WiMAX software modem on Open Multimedia Application Platform (OMAP) System on Chip (SoC) and Field Programmable Gate Array (FPGA). OMAP SoC is composed of ARM processor and Digital Signal Processor (DSP). ARM processor supports Single Instruction Multiple Data (SIMD) instruction which could operate on a vector of data with a single instruction and DSP is powerful image and video accelerators. For this reason, we suggest the possibility of SDR technology in the mobile handset. In order to verify the performance of the mobile WiMAX receiver, we measure the software modem runtime respectively. The experimental results show that the proposed receiver is able to do real-time signal processing.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.1
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• pp.7-13
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• 2011

According to increasing of data transfer rate, printed circuit board (PCB) is required improvement of transmission speed. Optical PCB and its packaging technology can be one of the solutions that overcome the limitations of conventional electrical PCB. The data transmission capacity will be increased 10 Tbps at 2015. To this end, studies on various OPCB technologies are being conducted. For cost-effective and high- performance OPCB, studies of optical coupling by polymer replication process are conducted. In this work, optical waveguide and optical fiber array block were sequentially fabricated by polymer pattern replication method. Using this method we successfully demonstrate low loss optical fiber coupling between optical waveguide and optical fiber arrays. And researches on flip chip bonding process and using electro-optic connectors for packaging are conducted.

• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.1787-1790
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• 2003

In this paper. we proposed a hardware(H/W) structure which can compress the video and embed the watermark in real time operation and implemented it into a FPGA platform using VHDL(VHSIC Hardware Description Language). All the image processing element to process both compression and reconstruction in a FPGA were considered each of them was mapped into H/W with the efficient structure for FPGA. The global operations of the designed H/W consists of the image compression with the watermarking and the reconstruction, and the watermarking operation is concurrently operated with the image compression. The implemented H/W used the 59％(12943) LAB(Logic Array Block) and 9％(28352) ESB(Embedded System Block) in the APEX20KC EP20K600CB652-7 FPGA chip of ALTERA, and stably operated in the 70㎒ clock frequency over. So we verified the real time operation, 60 fields/sec(30 frames/sec).

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.2
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• pp.125-134
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• 1994

This paper proposes a new top-down technology mapping algorithm for minimizing the chip area and the path delay time of lookup table-based field programmable gate array(FPGA). First, we present the decomposition and factoring algorithm using common subexpre ssion which minimizes the number of basic logic blocks and levels instead of the number of literals. Secondly, we propose a cube packing algorithm considering the decomposition of gates which exceed m-input lookup table. Previous approaches perform the cube packing and the gate decomposition independently, and it causes to increase the number of basic logic blocks. Lastly, the efficiency.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.8
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• pp.1-7
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• 1997

In tis paper, w eproposed a modeling for direct-sequence spread communication base band modem in RT-level VHDL and implemented in a one-chip VLSI and tested. The transmitter modulates with DQPSK modulation method and spreads a modulated signal with 32-bit PN code into 1.152MHz. The receiver de-spreads a signal using 32-tap matched filter and recovers with DQPSK demodulation method. The digital frequency synthesizer generates the sine signal and the cosine signal of 2.304MHz with ROM tables in the size of 7$\^$*/256 and 6$\^$*/256, respectively. The implemented VLSI has been verified a BER with 10$\^$-4/ at E$\_$b//N$\_$o/ of 13dB with a SPW fixed design model and fabricated in the 0.8.mu.m KG6423 gate array with a VHDL model.

• Proceedings of the KSME Conference
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• 2000.04a
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• pp.873-878
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• 2000

Semiconductor packaging technology is changed rapidly according to the trends of the micro miniaturization of multimedia and information equipment. For I/O limitation and fine pitch limitation, DIP and SOP/QFP are replaced by BGA/CSP. This is one of the surface mount technology(SMT). Solder ball is bumped n the die pad and connected onto mounting board. In ball bump formation, vacuum suction type ball alignment process is widely used, However this type has some problems such as ionization, static electricity and difficulty of fifo(first-input first-out) of solder balls. Seesaw type is reducing these problems and has a structural simplicity and economic efficiency. Ball cartridge velocity and ball aligned plate angle are Important variables to improve the ball alignment Process. In this paper, seesaw-type CSP solder ball loader is developed and the optimal velocity and plate angle are proposed.

• The Journal of the Acoustical Society of Korea
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• v.24 no.2E
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• pp.38-45
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• 2005

The noise reduction of the In-The-Ear (ITE) hearing aid (HA) can be achieved by arrays of microphones. Each of the right and the left ears was assumed to have two HA microphones. These arrays of HA microphones produce particular patterns of directivity by some time delay between two microphones. The directivity pattern geometrically increase the S/N ratio. The boundary element method (BEM) was used for the three dimensional simulation of the HA directivity pattern with the two pairs' microphone arrays. The separation between two microphones was fixed to 10 mm. The time delay between the two microphones was calculated to produce the most narrow directivity pattern in the fore front of the head. The variation of the time delay was examined in accordance with input frequencies. This numerical analysis may be then applied for the calculation of the time delay parameter of the digital hearing aid DSP chip.

• Bioinformatics and Biosystems
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• v.2 no.2
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• pp.71-74
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• 2007

Cell phenotypes are determined by groups of functionally related genes. Microarray profiling of gene expression provides us response of cellular state to its perturbation. Several methods for uncovering a cellular network show reliable network reconstruction. In this study, we present reconstruction of genetic regulatory network of inflammation bowel disease in human peripheral blood mononuclear cell. The microarray based on Affymetrix Gene Chip Human Genome U133 Array Set HG-U133A is processed and applied network reconstruction algorithm, ARACNe. As a result, we will show that inferred network composed of 450 nodes and 2017 edges is roughly scale-free network and hierarchical organization. The major hub, CCNL2 (cyclin A2), in inferred network is shown to be associated with inflammatory function as well as apoptotic function.