• ETRI Journal
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• v.35 no.2
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• pp.340-343
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• 2013

A novel bumping process using solder bump maker is developed for the maskless low-volume solder on pad (SoP) technology of fine-pitch flip chip bonding. The process includes two main steps: one is the aggregation of powdered solder on the metal pads on a substrate via an increase in temperature, and the other is the reflow of the deposited powder to form a low-volume SoP. Since the surface tension that exists when the solder is below its melting point is the major driving force of the solder deposit, only a small quantity of powdered solder adjacent to the pads can join the aggregation process to obtain a uniform, low-volume SoP array on the substrate, regardless of the pad configurations. Through this process, an SoP array on an organic substrate with a pitch of $130{\mu}m$ is successfully formed.

• Molecules and Cells
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• v.22 no.3
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• pp.254-261
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• 2006

DNA microarray is a powerful tool for high-throughput analysis of biological systems. Various computational tools have been created to facilitate the analysis of the large volume of data produced in DNA microarray experiments. Normalization is a critical step for obtaining data that are reliable and usable for subsequent analysis such as identification of differentially expressed genes and clustering. A variety of normalization methods have been proposed over the past few years, but no methods are still perfect. Various assumptions are often taken in the process of normalization. Therefore, the knowledge of underlying assumption and principle of normalization would be helpful for the correct analysis of microarray data. We present a review of normalization techniques from single-labeled platforms such as the Affymetrix GeneChip array to dual-labeled platforms like spotted array focusing on their principles and assumptions.

• Journal of Power Electronics
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• v.6 no.2
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• pp.114-120
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• 2006

This paper compares two types of direct torque controllers for permanent magnet synchronous motors(PMSMs). These controllers both use a single-chip FPGA(Field Programmable Gate Array) but have differing hardware configurations. One of the controllers was constructed by programming a soft-core CPU and hardware logic circuits written in VHDL(Very high speed IC Hardware Description Language), while the other was constructed of only hardware logic circuits. The characteristics of these two controllers were compared in this paper. The results show the controller constructed of only hardware logic circuits was able to shorten the control period and it was able to suppress the low torque ripple.

• Journal of Electrical Engineering and Technology
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• v.7 no.2
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• pp.221-224
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• 2012

We propose a Readout Integrated Circuit (ROIC), which applies a fixed current bias sensing method to the input stage in order to simplify the circuit structure and the infrared sensor characteristic control. For the sample-and-hold stage to display and control a signal detected by the infrared sensor using a two-dimensional (2D) focal plane array, a differential delta sampling (DDS) circuit is proposed, which effectively removes the FPN. In addition, the output characteristic is improved to have wider bandwidth and higher gain by applying a two-stage variable gain amplifier (VGA). The output characteristic of the proposed device was 23.91 mV/$^{\circ}C$, and the linearity error rate was less than 0.22%. After checking the performance of the ROIC using HSPICE simulation, the chip was manufactured and measured using the SMIC 0.35 um standard CMOS process to confirm that the simulation results from the actual design are in good agreement with the measurement results.

• ETRI Journal
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• v.38 no.3
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• pp.417-424
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• 2016

In this paper, an accurate characterization of a fabricated X-band transmit/receive module is described with the process of generating control data to correct amplitude and phase deviations in an active electronically scanned array antenna unit. In the characterization, quantization errors (from both a digitally controlled attenuator and a phase shifter) are considered using not theoretical values (due to discrete sets of amplitude and phase states) but measured values (of which implementation errors are a part). By using the presented procedure for the characterization, each initial control bit of both the attenuator and the phase shifter is closest to the required value for each array element position. In addition, each compensated control bit for the parasitic cross effect between amplitude and phase control is decided using the same procedure. Reduction of the peak sidelobe level of an array antenna is presented as an example to validate the proposed procedure.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.28 no.8 s.227
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• pp.1135-1139
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• 2004

This paper presents a microextractor for the separation of DNA molecules by their sizes. The DNA microextractor immobilizes the DNA molecules of specific size in the micropillar array by adjusting the period of the crossed electric field, thus providing a starting-point independent target DNA extraction method without separation process monitoring. The DNA microextractor has been fabricated by a three-mask micromachining process. The velocity of three different DNA molecules has been measured at the electric field of E=5V/0.8cm in the fabricated DNA microextractor, resulting in the reorientation times of $4.80{\pm}0.44sec,\;7.12{\pm}0.75sec$, and $9.88{\pm}0.30sec$ for ${\lambda}$ DNA, micrococcus DNA, and T4 DNA, respectively. T4 DNA is trapped in the micropillar array when the crossed electric field of 5V/0.8cm is applied alternately at a 10 second time interval. The present DNA microextractor filters the DNA in a specific size range by adjusting the magnitude and/or the period of the crossed electric field applied in the micropillar array.

• Journal of Sensor Science and Technology
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• v.25 no.5
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• pp.349-353
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• 2016

Recently, research on bolometer-type uncooled infrared image sensor which is made for industrial applications has been increasing. In general, it is difficult to calibrate fixed pattern noise (FPN) of bolometer array. In this paper, average-current calibration algorithm is presented for reducing bolometer resistance offset. A resistor which is produced by standard CMOS process, on the average, has a deviation. We compensate for deviation of each resistor using average-current calibration algorithm. The proposed algorithm has been implemented by a chip which is consisted of a bolometer pixel array, average current generators, current-to-voltage converters (IVCs), a digital-to-analog converter (DAC), and analog-to-digital converters (ADCs). These bolometer-resistor array and readout circuit were designed and manufactured by $0.35{\mu}m$ standard CMOS process.

• The Transactions of the Korea Information Processing Society
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• v.6 no.12
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• pp.3662-3674
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• 1999

This paper addresses some design issues for establishing the optimal number of spare units in array systems manufactured using fault-tolerant multichip modules(MCM's) for massively parallel computing(MPC). We propose a new quantitative approach to an optimal cost-effective MCM system design under yield and reliability constraints. In the proposed approach, we analyze the effect of residual redundancy on operational reliability of fault-tolerant MCM's. In particular, the issues of imperfect support circuitry, chip assembly yield and array topology are investigated. Extensive parametric results for the analysis are provided to show that our scheme can be applied to design ways using MCM's for MPC applications more efficiently, subject to yield and reliability constraints.

• ETRI Journal
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• v.40 no.6
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• pp.693-698
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• 2018

This paper presents a true-time delay (TTD) using a commercial $0.13-{\mu}m$ CMOS process for wideband phased-array antennas without the beam squint. The proposed TTD consists of four wideband distributed gain amplifiers (WDGAs), a 7-bit TTD circuit, and a 6-bit digital step attenuator (DSA) circuit. The T-type attenuator with a low-pass filter and the WDGAs are implemented for a low insertion loss error between the reference and time-delay states, and has a flat gain performance. The overall gain and return losses are >7 dB and >10 dB, respectively, at 2 GHz-18 GHz. The maximum time delay of 198 ps with a 1.56-ps step and the maximum attenuation of 31.5 dB with a 0.5-dB step are achieved at 2 GHz-18 GHz. The RMS time-delay and amplitude errors are <3 ps and <1 dB, respectively, at 2 GHz-18 GHz. An output P1 dB of <-0.5 dBm is achieved at 2 GHz-18 GHz. The chip size is $3.3{\times}1.6mm^2$, including pads, and the DC power consumption is 370 mW for a 3.3-V supply voltage.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.34 no.1
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• pp.8-15
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• 2021

Micro-LEDs can be applied to various parts of a product. However, it has disadvantages compared to general LEDs in large displays such as low efficiency, intensity, and contrast ratio, among others, owing to their short history of study. The simulations were carried out using ray-tracing software to investigate the change in light intensity and light distribution according to pattern shapes on the sapphire substrate of the flip-chip micro-LED (FC μ-LED) array. Three patterns-concave square patterns, convex square patterns, and Ag coated convex patterns-which existed on the opposite side of FC μ-LEDs (115 ㎛ × 115 ㎛) array, were applied. The intensity of FC μ-LEDs on the center of the receivers depends on the pattern depth with shape. The concave square patterns having FC μ-LEDs arrays show that decreasing intensity as the patterns depth. On the contrary, the convex square patterns having FC μ-LEDs arrays shows that increasing intensity as the patterns depth. In addition, the highest intensity shows that FC μ-LEDs having Ag-coated convex patterns on the opposite side of sapphire lead to a reduction in light crosstalk owing to the Ag film.