• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.1
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• pp.20-30
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• 2001

A 1.8V $650{\;}\textrm{mm}^2$ 4Gb DRAM having $0.10{\;}\mu\textrm{m}^2$ cell size has been successfully developed using 0.11 $\mu\textrm{m}$DRAM technology. Considering manufactur-ability, we have focused on developing patterning technology using KrF lithography that makes $0.11{\;}\mu\textrm{m}$ DRAM technology possible. Furthermore, we developed novel DRAM technologies, which will have strong influence on the future DRAM integration. These are novel oxide gap-filling, W-bit line with stud contact for borderless metal contact, line-type storage node self-aligned contact (SAC), mechanically stable metal-insulator-silicon (MIS) capacitor and CVD Al process for metal inter-connections. In addition, 80 nm array transistor and sub-80 nm memory cell contact are also developed for high functional yield as well as chip performance. Many issues which large sized chip often faces are solved by novel design approaches such as skew minimizing technique, gain control pre-sensing scheme and bit line calibration scheme.

• Proceedings of the KIEE Conference
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• 2003.10a
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• pp.300-302
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• 2003

This research aims to develop the multi-channel type label-free DNA chip that has the above characteristics and be able to solve the problems. At first, we fabricated a high integrated type DNA chip array by lithography technology. It is able to detect a various genes electrochemically after immobilization of a various probe DNA and hybridization of label-free target DNA on the electrode s simultaneously.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.297-300
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• 2002

Application of electronic nose and PLD chip design was developed to be used in gas discrimination system for limited kinds of gas. An array of 4 metal oxide gas sensors with different selectivity patterns were used in order to measure gases. BP(Back Propagation) algorithm was designed and implemented on CPLD of two hundred thousand gate level chips by VHDL language for processing input signals from 4 kinds of gas sensors. This module successfully discriminated 4 kinds of gases and displayed the results on LCD and LED. The developed module could be used for various applications in the field of food process control and alcohol judgment.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1141-1144
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• 2003

For proper communication with various types of IC-Card, multiple IC-Card interface complying with the IC-Card standard (ISO7816) is embedded and realized as a peripheral on the 32-bit RISC based system-on-a-chip. It provides the generation of either 3.3V or 5V power supply for the operation of the inserted IC-Card as well. IC-Card interface is divided into an analog front-end (AFE) and a digital back-end (DBE). The embedded DC-DC converters suitable for driving IC-Cards are incorporated in the AFE. The chip design for multiple IC-Card interface is implemented on a standard 0.35${\mu}{\textrm}{m}$ triple-metal double-poly CMOS process and is packaged in a 352-pin plastic ball grid array (PBGA). The total gate count is about 400,000, excluding the internal memory. Die area is 7890${\mu}{\textrm}{m}$ $\times$ 7890${\mu}{\textrm}{m}$.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1996.04a
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• pp.53-57
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• 1996

The side burrs and shape distortion resulting from the micromachining of an array of V-shape microgrooves in optical components were experimentally invesigated and a simplified model for their formation is proposed. Burr/shpae distortion should be kept to a minimum level since they degrade the characteristics and performance of these parts. The focus of this study is on the influence of depth of cut and workpiece material. The workpiece materials use were brass, bronze and copper. From the obsevation of the chip shape and burr/shape distortion, the proposed model, that the compressive force at the cutting edge causess the ductile uncut chip material to flow plastically outward toward the free surface to result in a burr, was verified.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.368-371
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• 1999

In this paper, we propose a neural network processor architecture with on-chip learning and with reconfigurability according to the data dependencies of the algorithm applied. For the neural network model applied, the proposed architecture can be configured into either SIMD or SRA(Systolic Ring Array) without my changing of on-chip configuration so as to obtain a high throughput. However, changing of system configuration can be controlled by user program. To process activation function, which needs amount of cycles to get its value, we design it by using PWL(Piece-Wise Linear) function approximation method. This unit has only single latency and the processing ability of non-linear function such as sigmoid gaussian function etc. And we verified the processing mechanism with EBP(Error Back-Propagation) model.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.376-379
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• 1999

The wavelet transform chip is implemented with Daubechies' 4 tap filter. It works at 20MHz in Field Programmable Gate array (FPGA) implementation of Quadrature Mirror Filter(QMF) Lattice Structure. In this paper, the structure contains taro-channel quadrature mirror filter, data format converter(DFC), delay control unit(DCU), and three 20$\times$8 bits real multiplier. The structures for the DFC and DCU need to he regular and scalable, require minimum number of regular, and thereby lead to an efficient and scalable architecture for the Discrete Wavelet Transform(DWT). These results present the possibility that it can be used in Digital Signal Processing(DSP) application faster than Fourier transform at small area with lour cost.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2004.10a
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• pp.500-504
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• 2004

The bio-micro pin has been usually used for the biochemistry analysis. The manufacturing capability of the micro-pin and the their array with the effective and low-cost way is very important and it gives great economical benefits to developers. The micro-pin is composed of the sample channel for holding the liquid with the fixed volume, the flat tip which determines the printing quality and the pin head for preventing the rotation of the pin in the holder. In this study, we have manufactured newly designed micro-pins by the wire-EDM process with special jigs, and analyzed liquid holding and printing characteristics with respect to the variation of the shape and the tip size of the micro-pin.

• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.1979-1981
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• 2002

새로운 방식의 일체형 flexible sensor module을 제작하였다. MEMS공정을 이용하여 제작된이 센서 모듈은 배선기판은 물론 strain sensor 역시 임의의 곡면에 실장을 위해 자유로운 굽힘이 가능하도록 제작되었다. 실리콘웨이퍼에 구현된 piezoresistor 스트레인 센서는 release-etch 방법을 통해 웨이퍼로부터 분리되어, 폴리이미드를 기판으로 하는 Flexible Sensor Array Module로 완성되었다. 소자와 기판을 따로 제작한 후 조립하는 기존의 방식에 비해, 웨이퍼 위에서 flexible 기판을 형성하여 수율이 높고 사진공정의 정밀도를 그대로 보전한 기판과 센서 어레이의 패키징이 가능하였으며, 칩을 기판에 실장하기 위한 정밀한 조립공정도 불필요하였다. 폴리이미드 기판은 전기도금을 통해 회로를 구성하여 1단계 패키징 (die to chip carrier)과 2단계 패키징 (chip to substrate)을 웨이퍼 레벨에서 완성하였다. 마지막으로 불산 용액을 통해 희생층을 제거함으로서 웨이퍼로 부터 센서어레이 모듈을 분리 하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.05a
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• pp.65-70
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• 2006

In this study, a DNA chip with a microelectrode array was fabricated using microfabrication technology. Several probe DNAs consisting of mercaptohexyl moiety at their 5 end were immobilized on the gold electrodes by DNA arrayer. Then target DNAs were hybridized and reacted with Hoechst 33258, which is a DNA minor groove binder and electrochemically active dye. Linear sweep voltammetry or cyclic voltammetry showed a difference between target DNA and control DNA in the anodic peak current values. It was derived from Hoechst 33258 concentrated at the electrode surface through association with formed hybrid. It suggested that this DNA chip could recognize the sequence specific genes.