• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.10a
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• pp.882-884
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• 2005

A new rectangular shape microlens array having high sag for solid-state lighting is presented. Proposed microlens, which has high sag, over $375{\mu}m$ and large diameter, over 3 mm can enormously enhance output optical extraction efficiency. Rectangular shape of microlens can maximize the fill factor of light-emitting-diode (LED) package and minimize the optical loss at the same time. This wafer level microlens array is fabricated on LED package. It has many advantages in optical properties, low cost, high aligning accuracy, and mass production.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.509-512
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• 2004

This paper proposed a new solid State Relay(SSR) structure that can replace the conventional SSR as a power IC. The photodiode arrays, the main part of this structure, were designed and integrated in the same power It chip with the output parts, LDMOSFET and BJT, on a SOI substrate. The fabrication of this input part shared the same output LDMOSFET fabrication processs, except the additional deposition of Silicon nitride($Si_3N_4$) for the photo-detection part. According to LED illumination intensites and photo detecting areas, we could obtain voltage of 0.49V ${\~}$0.52V and current of 5.5uA ${\~}$ 108uA respectively from the fabricated unit photodiode. The maximum value of the voltage and the current we could obtain from the photodiode array were 3.58V and 24.4uA respectively, and the voltage was enough to operate the output LDMOSFET

• Transactions of the Korean Society of Machine Tool Engineers
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• v.16 no.3
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• pp.50-55
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• 2007

The purpose of this research is to enhance the luminance of the LED and to improve the implementation of color by mounting an array lens on the LED without special technology in process. The workmanship of key components considering the economical efficiency and the injection molding technology for high quality of the product are essential to achieve it. In this paper, the mold was computer-aided was designed and manufactured by CAM software (NX4) and high speed machining center. the applied final machining conditions were 3,000-5,000mm/min feed speed, 15,000-25,000rpm and ${\Phi}0.3mm$ ball end-mill. And the Flow analysis was performed using the mold flow software(MPI) in order to get uniformity of resin. Injection conditions acquired by the flow analysis and the injection experiment are as follows. The cylinder temperature is $220-260^{\circ}C$, the mold temperature is $70-80^{\circ}C$, the injection time is about 1.2sec, the injection pressure and velocity is each 7.8-14.7Mpa, and the injection velocity is 0.8-1.2m/sec.

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1655-1666
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• 2015

This paper proposes a new approach of Field Programmable Gate Array (FPGA) controlled digital implementation of shunt active power filter (SAPF) under steady state and dynamic operations. Typical implementations of SAPF uses microprocessor and digital signal processor (DSP) but it limited for complex algorithm structure, absence of feedback loop delays and their cost can be exceed the benefit they bring. In this paper, the hardware resources of an FPGA are configured and implemented in order to overcome conventional microcontroller or digital signal processor implementations. This proposed FPGA digital implementation scheme has very less execution time and boosts the overall performance of the system. The FPGA controller integrates the entire control algorithm of an SAPF, including synchronous reference frame transformation, phase locked loop, low pass filter and inverter current controller etc. All these required algorithms are implemented with a single all-on chip FPGA module which provides freedom to reconfigure for any other applications. The entire algorithm is coded, processed and simulated using Xilinx 12.1 ISE suite to estimate the advantages of the proposed system. The coded algorithm is also defused on a single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype and experimental results thus obtained match with simulated counterparts under the dynamic state and steady state operating conditions.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.69-74
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• 2013

In this paper, the impact of integrating large number of I/O (Input-Output) and Core power Delivery Network (PDN) on a 6 layers Flip-Chip Ball Grid Array (FCBGA) package is investigated. The impact of core induced supply noise on high-speed I/O interfaces, and high-speed I/O interface's supply noise coupling to adjacent high-speed I/O interfaces' jitter impact are studied. Concurrent stress validation software is used to induce SSO noise on each individual I/O interfaces; and at the same time; periodic noise is introduced from Core PDN into the I/O PDN domain. In order to have the maximum coupling impact, a prototype package is designed to merge the I/O and Core PDN as one while impact on jitter on each I/O interfaces are investigated. In order to understand the impact of the Core to I/O and I/O to I/O noise, the on-die noise measurements were measured and results were compared with the original PDN where each I/O and Core PDN are standalone and isolated are used as a benchmark.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.5
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• pp.117-126
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• 1989

In this paper, a new placement algorithm for gate array lay out design is proposed. The proposed algorithm can treat the variable-sized macrocells and by considering the I/Q pad locations, the routing between I/Q pads and the internal region of a chip can be automated effectively. The algorithm is composed of 3 parts. which are initial partitioning, initial placement and placement improvement. In the initial placement phase, a given circuit is partitioned into 5 sub-circuits, by clustering method with considers connectivities of cells not only with I/Q pads but also with related partitioned groups is used repeatedly to assign a unique position to each cell. In the placement improvement phase, the concept of probabilistic wiring density is introduced, and cell moving algorithm is proposed to make the density in a chip even.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.2
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• pp.168-173
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• 2008

In this paper, we have designed transmit/receive Module for X band which can be applied to active phase array radar system. AESA(active electrically beam steered array) is able to transmit high power as like TWTA with composition of TH Module and steer a main beam faster than mechanically steering system. The proposed structure of T/R Module for X band is brick type for physical structure, common leg structure electrically and small size design as MCM(multi chip module). The results show that the characteristic of proposed T/R module can fully cover the specification of required military radar application.

• Journal of Sensor Science and Technology
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• v.14 no.6
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• pp.430-437
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• 2005

In this paper, we proposed a biologically inspired light-adaptive edge detection circuit based on the human retina. A saturating resistive network was suggested for light adaptation and simulated by using HSPICE. The light adaptation mechanism of the edge detection circuit was quantitatively analyzed by using a simple model of the saturating resistive element. A light-adaptive capability of the edge detection circuit was confirmed by using the one-dimensional array of the 128 pixels with various levels of input light intensity. Experimental data of the saturating resistive element was compared with the simulated results. The entire capability of the edge detection circuit, implemented with the saturating resistive network, was investigated through the two-dimensional array of the $64{\times}64$ pixels

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.8
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• pp.940-945
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• 2008

In this paper, we have designed the Brick Transmit/Receive Module for K-band which can be applied to active phase array radar system. The proposed structure of T/R Module for K band is brick type for MCM(Multi Chip Module) form and the satisfaction of tile type T/R Module can apply to structure of cavity and main characteristic. The fabricated brick type T/R Module confirmed the main characteristic for electrical goal performance in test and this structure can be applied to active phase array radar.

• Current Optics and Photonics
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• v.4 no.3
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• pp.229-237
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• 2020

In this study, a beam-coupling system is designed to improve the coupling efficiency of achip-integrated spectrometer when the waveguide is arranged in a linear and discrete manner. In the proposed system the beam is shaped to be anti-Gaussian, to deposit adequate energy in the edge waveguides. The beam is discretely coupled to the corresponding waveguide by a microlens array, to improve the coupling efficiency, and is compressed by a toroidal lens to match the linear discrete waveguides. Based on the findings of this study, the coupling efficiency of the spectrometer is shown to increase by a factor of 2.57. Accordingly, this study provides a reference basis for the improvement of the coupling efficiency of other similar spectrometers.