• 한국정보전자통신기술학회논문지
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• 제1권2호
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• pp.91-98
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• 2008

국내 지상파 DMB방송 표준에서는 2003년 말 국제 표준으로 제정한 MPEG-4 BSAC(Bit Sliced Arithmetic Coding) 오디오 복호화 방식를 표준으로 채택하였다. 본 논문에서는 MPEG-4 BSAC 오디오 복호화기의 주요 도구 및 모듈에 대해 32비트 고정소수점 연산으로 구현하고 ARM926EJ-S 프로세서에 인라인 어셈블리(Inline Assembly)를 적용하여 최적화 한다. 최적화에 대해 본 논문에서는 RISC프로세서인 ARM926EJ-S의 Core Cycle을 가장 높게 발생시키는 곱셈 및 MAC(Multiply And Accumulation)연산에 집중한다. 그리고 각 모듈 및 도구에서 빈번히 발생하는 곱셈 연산과 MAC연산의 처리를 효율적으로 하기 위하여 대상 프로세서인 ARM926EJ-S에서 사용 가능한 ARMv5용 어셈블리 명령어를 분석하여 사용한다. 최적화된 결과는 MIPS(Million Instruction Per Second)를 기준으로 평가한다. 구현 결과는 96kbps BSAC bitstream을 65MHz CPU clock에서 실시간으로 디코딩할 수 있음을 보여준다.

• 한국게임학회 논문지
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• 제13권6호
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• pp.43-52
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• 2013

경로 탐색은 인공지능의 매우 중요한 요소 중의 하나이며, 여러 분야에서 두루 쓰이는 과정이다. 경로 탐색은 매우 많은 연산이 필요하기 때문에 성능에 매우 중대한 영향을 미친다. 이를 해결하기 위해서 연산량을 줄이는 방식의 연구가 많이 진행되었고, 대표적으로 A* 알고리즘이 있으나 불필요한 연산이 있어 효율성이 떨어진다. 본 논문에서는 A* 알고리즘 중 연산 비용이 높은 노드 탐색 수 등 연산량을 줄이기 위해서 가중치 기반의 선수행 A* 알고리즘을 새롭게 제안한다. 제안한 알고리즘의 효율성을 측정하기 위해 시뮬레이션을 구현하였으며, 실험 결과 가중치를 이용하는 방법이 일반적인 방법보다 약 1~2배 높은 효율을 보였다.

• Smart Structures and Systems
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• 제14권6호
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• pp.1131-1150
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• 2014

One of the issues in extending the range of applicable problems of real-time hybrid simulation is the computation speed of the simulator when large-scale computational models with a large number of DOF are used. In this study, functionality of real-time dynamic simulation of MDOF systems is achieved by creating a logic circuit that performs the step-by-step numerical time integration of the equations of motion of the system. The designed logic circuit can be implemented to an FPGA-based system; FPGA (Field Programmable Gate Array) allows large-scale parallel computing by implementing a number of arithmetic operators within the device. The operator splitting method is used as the numerical time integration scheme. The logic circuit consists of blocks of circuits that perform numerical arithmetic operations that appear in the integration scheme, including addition and multiplication of floating-point numbers, registers to store the intermediate data, and data busses connecting these elements to transmit various information including the floating-point numerical data among them. Case study on several types of linear and nonlinear MDOF system models shows that use of resource sharing in logic synthesis is crucial for effective application of FPGA to real-time dynamic simulation of structural response with time step interval of 1 ms.

• 한국정보과학회논문지:시스템및이론
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• 제30권12호
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• pp.749-755
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• 2003

최근 레지듀 수체계를 기반으로 하는 컴퓨터 영상처리, 음성출력 등의 디지털 신호처리 하드웨어에 관한 연구가 고속저가의 하드웨어 구현에 크게 기여하고 있다. 본 논문에서는 모듈라이$(2^k-1, 2^k, 2^k+1)$를 사용하여 RNS에서 WNS로 WNS에서 RNS로 변환하는 방법을 통해 승산기를 설계 및 구현한다. 이는 CRT 변환을 중첩다중비트 주사기법을 접목한 시뮬레이션을 통해, 기존의 방법보다 속도가 빠르다는 것을 알 수 있고, 이는 RNS의 병렬처리와 캐리부재의 연산특성 때문임을 알 수 있다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제9권8호
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• pp.3103-3120
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• 2015

This paper presents a single-phase energy metering chip with built-in calibration function to measure electric power quantities. The entire chip consists of an analog front end, a filter block, a computation engine, a calibration engine, and an external interface block. The key design issues are how to reduce the implementation costs of the computation engine from repeatedly used arithmetic operations and how to simplify calibration procedure and reduce calibration time. The proposed energy metering chip simplifies the computation engine using time-division multiplexed arithmetic units. It also provides a simple and fast calibration scheme by using integrated digital calibration functionality. The chip is fabricated with 0.18-μm six-layer metal CMOS process and housed in a 32-pin quad-flat no-leads (QFN) package. It operates at a clock speed of 4096 kHz and consumes 9.84 mW in 3.3 V supply.

• 대한안전경영과학회지
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• 제14권3호
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• pp.135-141
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• 2012

This study was conducted to evaluate the characteristics of exposure to asbestos for ship repair workers in Korea by a systematic review. The number of articles studying asbestos exposure levels from ship repair workplaces was found to be 4. All asbestos concentration reported as either geometric mean and geometric standard deviation or ranges were transformed to arithmetic mean to estimate exposure level. In addition, weighted arithmetic means(WAMs) were calculated by weighing of the different number of samples. The WAM concentrations were 2.746 f/cc during asbestos dismantling work, 0.034 f/cc before asbestos dismantling work and 0.065 f/cc after working respectively. The maximum airborne concentration of asbestos during asbestos removal work was 7.02 f/cc which was 70 times higher than the occupational exposure limit of Korea, 0.1 f/cc. This study recommends that retrospective exposure to asbestos based on various ship types and operations should be assessed.

• 전기전자학회논문지
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• 제21권3호
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• pp.280-283
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• 2017

HEVC(high efficiency video coding)의 엔트로피 코딩 방식인 CABAC(context-based adaptive binary arithmetic coding)에서는 각 구문 요소의 발생 확률을 추정하는 문맥 모델이 사용된다. 본 논문에서는 CABAC 복호화에 필요한 문맥 모델러를 설계하고 이를 구현하였다. 초기화에 필요한 연산 숫자를 줄이고 속도를 높이기 위해 참조 테이블을 사용하였으며, HEVC의 표준 테스트 영상 및 표준 부호기 구성에 대해 12가지의 시뮬레이션을 수행하여 모두 성공적으로 동작하는 것을 확인하였다. 설계된 문맥 모델러를 0.18um에서 합성하였을 때의 최대 동작 주파수, 최대 처리율 및 게이트 수는 각각 200 MHz, 200 Mbin/s, 29,268 게이트이다.

• 정보학연구
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• 제9권4호
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• pp.49-55
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• 2006

In this paper, a new fragile watermarking algorithm for digital image is presented, which makes resolving the security and forgery problem of the digital image to be possible. The most suitable watermarking method that verifies the authentication and integrity of the digital image is the Wong's method, which invokes the hash function (MD5). The algorithm is safe because this method uses the hash function of the cryptology. The operations such as modulus, complement, shift, bitwise exclusive-or, bitwise inclusive-or are necessary for calculating the value of hash function. But, in this paper, an Arithmetic encoding method that only includes the multiplication operation is adopted. This technique prints out accumulative probability interval, which is obtained by multiplying the input symbol probability interval. In this paper, the initial probability interval is determined according to the value of the key, and the input sequence of the symbols is adjusted according to the key value so that the accumulative probability interval will depend on the key value. The integrity of the algorithm has been verified by experiment. The PSNR is above the 51.13db and the verifying time is $1/3{\sim}1/4$ of the verifying time of using the hash function (MD5), so, it can be used in the real-time system.

• ETRI Journal
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• 제42권4호
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• pp.596-607
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• 2020

Scaling is an important operation because of the iterative nature of arithmetic processes in digital signal processors (DSPs). In residue number system (RNS)-based DSPs, scaling represents a performance bottleneck based on the complexity of intermodulo operations. To design an efficient RNS scaler for special moduli sets, a body of literature has been dedicated to the study of the well-known moduli sets {2ⁿ - 1, 2ⁿ, 2ⁿ + 1} and {2ⁿ, 2ⁿ - 1, 2ⁿ⁺¹ - 1}, and their extension in vertical or horizontal forms. In this study, we propose an efficient programmable RNS scaler for the arithmetic-friendly moduli set {2^n+p, 2ⁿ - 1, 2ⁿ⁺¹ - 1}. The proposed algorithm yields high speed and energy-efficient realization of an RNS programmable scaler based on the effective exploitation of the mixed-radix representation, parallelism, and a hardware sharing technique. Experimental results obtained for a 130 nm CMOS ASIC technology demonstrate the superiority of the proposed programmable scaler compared to the only available and highly effective hybrid programmable scaler for an identical moduli set. The proposed scaler provides 43.28% less power consumption, 33.27% faster execution, and 28.55% more area saving on average compared to the hybrid programmable scaler.

• Progress in Superconductivity
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• 제8권2호
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• pp.181-185
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• 2007

For more than two decades Nb trilayer ($Nb/Al_2O_3/Nb$) process has been serving as the most stable fabrication process of the Josephson junction integrated circuits. Fast development of semiconductor fabrication technology has been possible with the recent advancement of the fabrication equipments. In this work, we took an advantage of advanced fabrication equipments in developing a superconducting Arithmetic Logic Unit (ALU) by using Nb trilayers. The ALU is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. We used DC magnetron sputtering technique for metal depositions and RF sputtering technique for $SiO_2$ depositions. Various dry etching techniques were used to define the Josephson junction areas and film pattering processes. Our Nb films were stress free and showed the $T{_c}'s$ of about 9 K. To enhance the step coverage of Nb films we used reverse bias powered DC magnetron sputtering technique. The fabricated 1-bit, 2-bit, and 4-bit ALU circuits were tested at a few kilo-hertz clock frequency as well as a few tens giga-hertz clock frequency, respectively. Our 1-bit ALU operated correctly at up to 40 GHz clock frequency, and the 4-bit ALU operated at up to 5 GHz clock frequency.