• ETRI Journal
• /
• v.29 no.4
• /
• pp.445-451
• /
• 2007

An adaptive modulation scheme is presented for multiuser orthogonal frequency-division multiplexing systems. The aim of the scheme is to minimize the total transmit power with a constraint on the transmission rate for users, assuming knowledge of the instantaneous channel gains for all users using a combined bit-loading and subcarrier allocation algorithm. The subcarrier allocation algorithm identifies the appropriate assignment of subcarriers to the users, while the bit-loading algorithm determines the number of bits given to each subcarrier. The proposed bit-loading algorithm is derived from the geometric progression of the additional transmission power required by the subcarriers and the arithmetic-geometric means inequality. This algorithm has a simple procedure and low computational complexity. A heuristic approach is also used for the subcarrier allocation algorithm, providing a trade-off between complexity and performance. Numerical results demonstrate that the proposed algorithms provide comparable performance with existing algorithms with low computational cost.

• Proceedings of the IEEK Conference
• /
• 2003.07e
• /
• pp.2192-2195
• /
• 2003

This parer proposes a power-line phase measurement algorithm which is based on the recursive implementation of sliding-DFT. Usage of the single DFT coefficient in the conventional sliding-DFT based power-line phase measurement brings a significant error propagation when implemented in hardware with finite word-length arithmetic operations. The proposed algorithm utilizes all the N-point DFT coefficients in the recursion. Performance degradation caused by the finite word- length implementation of the algorithm is analyzed and verified with computer simulations. The robustness of the proposed phase measurement algorithm against the erroneous implementation is also confirmed by the performance analysis and simulation.

• Proceedings of the IEEK Conference
• /
• 2002.07c
• /
• pp.1563-1566
• /
• 2002

A 16-bit adiabatic datapath for micro-power RISC processor is designed. The datapath is composed of a 3-read and 1-write multi-port adiabatic register file and an arithmetic and logic unit. A four-phase clock generator is also designed to provide supply clocks fer adiabatic circuits and the driving capability control scheme is proposed. All the clock line charge on the capacitive interconnections is recovered to recycle energy. Adiabatic circuits are designed based on efficient charge recovery logic(ECRL) and are implemented using a 0.35 fm CMOS technology. Functional and energy simulation is carried out to show the feasibility of adiabatic datapath. Simulation results show that the power consumption of the adiabatic datapath including supply clock generator is reduced by a factor of 1.4∼1.5 compared to that of the conventional CMOS.

• The Transactions of the Korean Institute of Electrical Engineers A
• /
• v.52 no.11
• /
• pp.647-654
• /
• 2003

As electrical power system has become complicated and enlarged to cope with the increasing electric demand, it has to be expected that higher speed, higher reliability, higher function and higher arithmetic ability in protective relay should be realized. Therefore, in this papers, by hardware design and implementation used DMA controller that transfer blocks of data to any location in the memory map without interfering with CPU operation, CPU utilization is increased effectively, as a result it made possible to implement multi-function digital protective relay which has high trust and high function of protection as well as control and metering for power transformers using single processor(DSP).

• Proceedings of the Korean Information Science Society Conference
• /
• 2002.04a
• /
• pp.16-18
• /
• 2002

고속 회로 합성에 있어서, Wallace 트리 스타일은 연산을 위한 가장 효율적인 수행 방식의 하나로 인식 되어졌다. 그러나, 이러한 방법은 빠른 곱셈기의 수행이나 여러가지 연산수행 에 있어, 입력 시그널을 고려하지 않은 일반적인 구조로 수행되어졌다. 본 논문은 연산기에 있어서 이러한 제한점을 극복하는 문제를 다룬다. 우리는 캐리-세이브 방법을 덧셈, 뺄셈, 곱셈 이 혼합되어 있는 일반적인 연산 회로에 적용한다. 그 결과 효율적인 회로를 생성하며, 시그널 들의 임의의 시그널 스위칭 변화에 대해 회로의 전력 소모를 최적화 한다. 우리는 이러한 최적화 방법을 여러 디지털 필터에 적용시켜 보았고 이는 기존의 비트 단위가 아닌 캐리-세이브 수행방법보다 상당한 양의 전력 소모의 향상을 보였다.

• Journal for History of Mathematics
• /
• v.16 no.3
• /
• pp.89-94
• /
• 2003

Though the concept of unique factorization was formulated in tile 19th century, Euclid already had considered the prime factorization of natural numbers, so called tile fundamental theorem of arithmetic. The unique factorization of algebraic integers was a crucial problem in solving elliptic equations and the Fermat Last Problem in tile 19th century On the other hand the unique factorization of the formal power series ring were a critical problem in the past century. Unique factorization is one of the idealistic condition in computation and prime elements and prime ideals are vital ingredients in thinking and solving problems.

• Proceedings of the IEEK Conference
• /
• 2002.06b
• /
• pp.157-160
• /
• 2002

This paper proposed a guideline for selecting the arithmetic circuit architecture. The guideline incorpo-rates the new concept of PDSP (power-delay-size product) and the weighting method. HSPICE simulations havc been performed to several full adders in order to prove the validity of the proposed guideline. We applied this guideline to select an optimized FA (full adder) architecture and successfully implemented the DAC's digital blocks.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• v.9 no.2
• /
• pp.795-798
• /
• 2005

In this paper, we analyses of additive crypto-module architecture for a sensor network. Recent research in sensor networks has raised security issues for small embedded devices. Security concerns are motivated by the development of a large number of sensor devices in the field. Limitations in processing power, battery life, communication bandwidth and memoryconstrain devices. A mismatch between wide arithmetic for security and embedded data buscombined with lack of certain operations. Then, we compared the architecture of crypto-module in this paper.

• Journal of Electrical Engineering and Technology
• /
• v.2 no.3
• /
• pp.312-319
• /
• 2007

The solution of the power flow is one of the most important problems in electrical power systems. These traditional methods such as Gauss-Seidel method and Newton-Raphson (NR) method have had drawbacks up to now such as initial values, abnormal operating solutions and divergences in heavy loads. In order to overcome theses problems, the power flow solution incorporating genetic algorithm (GA) is introduced in this paper. General operator of genetic algorithm, arithmetic crossover, and non-uniform mutation operator of GA are suggested to solve the power flow problem. While abnormal solution cannot be obtained by a NR method, multiple power flow solution can be obtained by a GA method. With a heavy load, both normal solution and abnormal solution can be obtained by a proposed method. In this paper, a floating number representation instead of the binary number representation is introduced for accuracy. Simulation results have been compared with traditional methods.

• Proceedings of the KIEE Conference
• /
• 2009.07a
• /
• pp.2119.1_2120.1
• /
• 2009

UWB(Ultra Wide Band)는 차세대 무선통신 기술로 무선 디지털펄스라고도 한다. GHz대의 주파수를 사용하면서도 초당 수천~수백만 회의 저출력 펄스로 이루어진 것이 큰 특징이다[1]. 기존 무선통신 기술의 양대 축인 IEEE 802.11과 블루투스 등에 비해 속도와 전력소모 등에서 월등히 앞서고 있으며, SoC(System on a Chip)의 저전력 구현에 대한 연구가 활발히 진행되고 있다. OFDM은 크게 FFT(Fast Fourier Transform) 블록, Interpolation /decimation 필터 블록, 비터비 블록, 변복조 블록, 등화기 블록 등으로 구성된다. 고속 시스템에서는 대역효율성이 우수한 OFDM(Orthogonal Frequency Division Multiplexing) 방식을 사용하고 있으며, OFDM 전송방식은 직렬로 입력되는 데이터 열을 병렬 데이터 열로 변환한 후에 부반송파에 실어 전송하는 방식이다. 이와 같은 병렬화와 부반송파를 곱하는 동작은 IFFT와 FFT로 구현이 가능한데, FFT 블록의 구현 비용과 전력소모를 줄이는 것이 핵심사항이라고 할 수 있다. 기존논문에서는 OFDM용 FFT 구조로 단일버터플라이연산자 구조, 파이프라인 구조, 병렬구조 등의 여러 구조가 제안되었다[2]. 본 논문에서는 Radix-8 FFT 알고리즘 기반의 New partial Arithmetic 저전력 FFT 구조를 제안하였다. 제안한 New partial Arithmetic 저전력 FFT구조는 곱셈기 대신 병렬 가산기를 이용 하여 지금까지 사용되는 FFT 구조보다 전력소모를 줄일 수 있음을 보였다.