• ETRI Journal
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• 제24권6호
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• pp.473-476
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• 2002

This letter proposes an efficient kernel-based partitioning algorithm for reducing area and power dissipation in combinational circuit designs using don't-care sets. The proposed algorithm decreases power dissipation by partitioning a given circuit using a kernel extracted from the logic. The proposed algorithm also reduces the area overhead by minimizing duplicated gates in the partitioned sub-circuits. The partitioned subcircuits are further optimized utilizing observability don't-care sets. Experimental results for the MCNC benchmarks show that the proposed algorithm synthesizes circuits that on the average consume 22.5% less power and have 12.7% less area than circuits generated by previous algorithms based on a precomputation scheme.

• 한국군사과학기술학회지
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• 제21권2호
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• pp.225-234
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• 2018

In this paper, we consider a problem of partitioning a search area into smaller rectangular regions, so that multiple platforms can conduct search operations independently without requiring unnecessary coordination among themselves. The search area consists of cells where each cell has some prior information regarding the probability of target existence. The detection probability in particular cell is evaluated by multiplying the observation probability of the platform and the target existence probability in that cell. The total detection probability within the search area is defined as the cumulative detection probability for each cell. However, since this search area partitioning problem is NP-Hard, we decompose the problem into three sequential phases to solve this computationally intractable problem. Additionally, we discuss a special case of this problem, which can provide an optimal analytic solution. We also examine the performance of the proposed approach by comparing our results with the optimal analytic solution.

• 전자공학회논문지C
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• 제35C권5호
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• pp.1-10
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• 1998

In this paper, a new hardware-software patitioning algorithm is presented, in which the system behavioral description containing a mixture of hardware and softwae components is partitioned into the hardware part and the software part. In this research, new techniques to optimally partition a mixed system under certain specified constaints such as performance, area, and delay, have been developed. During the partitioning process, the overhead due to the communication between the hardware and software parts are considered. New featues have been added to adjust the hierarchical level of partitioning. Power consumption, memory cost, and the effect of pipelining can also be considered during partitioning. Another new feature is the ability to partition a DSP system under throughput constraints. This feature is important for real time processing. The developed partitioning system can also be used to evaluate various design alternatives and architectures.

• 융합신호처리학회논문지
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• 제2권4호
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• pp.97-102
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• 2001

CAD(Computer-Aided Design)에서의 분할(partitioning)은 기능의 최적화를 위해 대상의 그룹화(grouping)로 레이아웃(layout)에 면적과 전파지연 최소화를 위해 함께 위치할 소자를 결정하는 문제 또는 스케쥴링이나 유닛 선택을 위한 HLS(high level synthesis)에서의 변수나 연산에 대한 집단화 (clustering) 문제들을 포함하여 분할 문제에서 해를 얻기 위해 Kernighan-Lin 알고리즘 Fiduccia Mattheyses heuristic, 시뮬레이티드 어닐링(simulated annealing)등의 방식이 이용된다. 본 논문에서는 회로 분할 문제에 대하여 유전 알고리즘(GA; genetic algorithm)을 이용한 해 공간 탐색(soultion space search)방식을 제안하였으며, 제안한 방식을 시뮬레이티드 어닐링 방식과 비교, 분석하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 C
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• pp.1067-1069
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• 1999

This paper presents a network reduction using weak coupling method. Weak coupling method of identifying coherent generator groups are proposed. The partitioning technique used in this paper is based on a property of sparse matrix factorization. When a matrix has been factorized, a system is divided into study area, boundary buses and external area. A reduction process for external system starts with the load bus elimination and coherent generator aggregation. An identification of coherent generator group, network partitioning and network reduction are presented.

• 한국통신학회논문지
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• 제25권8B호
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• pp.1477-1486
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• 2000

본 논문에서는 조합 논리 회로의 면적과 전력 소모를 낮추기 위한 효율적인 커널 기반의 분할 알고리듬을 제안 한다. 제안한 알고리듬은 커널을 이용하여 회로를 분할함으로써 회로의 전력 소모를 줄이고 분할된 회로들의 중복 되는 게이트를 최소화시켜 면적 overhead를 감소시킨다. MCNC 표준 테스트 회로에 대한 실험을 통하여 제안된 알고리듬이 면적과 전력소모면에 있어서 기존의 precomputation 회로 구조에 바탕을 둔 알고리듬에 비해 전력 소모는 평균 43.6% 면적은 평균30.7% 향상된 결과를 보인다.

• 한국환경과학회지
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• 제22권2호
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• pp.187-193
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• 2013

Dry matter allocation characteristics of Calystegia soldanella, grown in pots, was analysed to assess its plasticity in response to water-stressed conditions. As water was withheld leaf water potential between the two watering treatments was similar during the first 6 days, followed by a rapid decrease in water-stressed plants. The minimum leaf water potential was -1.50 MPa on day 15 and the maximum leaf water potential was about -0.5 MPa on day 0 in water-stressed plants. In well-watered plants leaf water potential was maintained almost consistently throughout the experiment. There was no significant difference in plant dry weight between the two watering treatments for 9 days after the start of experiment and that was remarkably increased thereafter, compared with that remained without any increase in water-stressed plants. In dry mass partitioning, however, the water-stressed plants showed a great plasticity, showing that there were 1.81, 1.35 and 0.81 times increase in root, stem and leaf, respectively. Dry mass partitioning in well-watered plants varied from 2% to 5%. The difference of dry mass partitioning between the two watering treatments was reflected in leaf mass per unit area (LMA) and root/shoot (R/S) ratio. LMA in water-stressed plants was lower than that in well-watered plants, while R/S ratio in water-stressed plants was higher in well-watered plants. This means that the water-stressed plants reduced its leaf area and increased dry mass partitioning into root and stem during the progress of soil drying. These results indicate that Calystegia soldanella inhabiting in sand dune cope with water stress with high plasticity which can adjust its dry mass partitioning according to soil water conditions.

• 정보처리학회논문지D
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• 제11D권1호
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• pp.23-30
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• 2004

공간 질의 크기에 대한 근사치를 구하기 위해서는 입력 데이터 공간을 분할한 후 분할된 영역에 대하여 질의 결과 크기를 추정한다. 본 논문에서는 데이터 편재가 심한 공간 데이터에 대한 질의 크기 추정의 문제를 논의한다. 공간을 분할하는 기법으로 관계 데이터베이스에서 많이 사용되는 너비 균등, 높이 균등 히스토그램에 해당되는 면적 균등, 개수 균등 분할에 대한 방법을 검토하고 공간 인덱싱에 기초한 공간 분할방법에 대해서 알아본다. 본 논문에서는 공간 순서화 기법인 힐버트 공간 채움 곡선을 이용한 공간 분할을 제안한다. 제안한 방법과 기존의 방법을 실제 데이터와 인위 데이터를 사용하여 편재된 공간 데이터에 대한 질의 결과 크기의 추정에 대한 정확도를 비교한다. 본 실험에서 힐버트 채움 곡선에 의한 공간 분할이 공간 질의 크기 버켓 수의 변화, 데이터 위치 편재도의 변화, 데이터 크기의 변화에 대해서 기존의 분할 방법보다 질의 결과 크기 추정에 대해서 우수한 성능을 보였다.

• 한국재료학회지
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• 제19권6호
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• pp.305-312
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• 2009

The effects of Quenching and Partitioning (Q&P) and Annealed Martensite (AM) heat treatment on the microstructure and tensile properties were investigated for 0.24C-0.5Si-1.5Mn-1Al steels. The Q&P steels were annealed at a single phase ($\gamma$) or a dual phase (${\gamma}+{\alpha}$), followed by quenching to a temperature between $M_s$ and $M_f$. Then, enriching carbon was conducted to stabilize the austenite through the partitioning, followed by water quenching. The AM steels were intercritically annealed at a dual phase (${\gamma}+{\alpha}$) temperature and austempered at $M_s$ and $M_s{\pm}50^{\circ}C$, followed by cooling in oil quenching. The dual phase Q&P steels showed lower tensile strength and yieldyield strength than those of the single phase Q&P steels, and tThe elongation for the dual phase Q&P steel was partitioning 100s higher than that of that for the single phase Q&P steels as the partitioning time was less than 100s up to partitioning 100s. For AM steels, the tensile/yield strength decreased and the total elongation increased as the austempering temperature increased. The stability of the retained austenite controlled the elongation for Q&P steels and the volume fraction of the retained austenite controlled the elongation for AM steels.

• 한국항공우주학회지
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• 제31권10호
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• pp.1-9
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• 2003

컴퓨팅 그리드 환경에서는 컴퓨팅 그리드 시스템을 구성하는 단위 시스템들의 성능이 균일하지 않기 때문에, 영역을 균등하게 분할하는 일반적인 로드밸런싱 기법을 적용하기가 적절하지 않다. 본 연구에서는 그래프 분할기법을 기반으로 하여, 컴퓨팅 그리드 시스템을 구성하는 단위 시스템들의 성능가중치를 계산하여 분할하는 2단계 영역 분할 기법을 제시하였다. 2단계 영역 분할 기법 시 발생하는 통신량의 증가는 그래프 분할기법인 WEVM을 적용하여 최소화 할 수 있었으며, 멀티 클러스터 환경과 WAN에서 타당성과 효율성을 검증해 보았다.