• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.3
• /
• pp.8-16
• /
• 1999

This paper describes a VLSI design of Reed-Solomon(RS) decoder using the modified Euclid algorithm, with the main theme focused on the $\textit{GF}(2^8)$. To get area-efficient design, a number of new architectures have been devised with maximal register and Euclidean ALU unit sharing. One ALU is shared to replace 18 ALUs which computes an error locator polynomial and an error evaluation polynomial. Also, 18 registers are shared to replace 24 registers which stores coefficients of those polynomials. The validity and efficiency of the proposed architecture have been verified by simulation and by FLEX$^TM$ FPGA implementation in hardware description language VHDL. The proposed Reed-Solomon decoder, which has the capability of decoding RS(208,192,17) and RS(182,172,11) for Digital Versatile Disc(DVD), has been designed by using O.6$\mu\textrm{m}$ CMOS TLM Compass$^TM$ technology library, which contains totally 17k gates with a core area of 2.299$\times$2.284 (5.25$\textrm{mm}^2$). The chip can run at 20MHz while the DVD requirement is 3.74MHz.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.44 no.4 s.316
• /
• pp.51-59
• /
• 2007

In this paper, we propose an efficient hardware architecture for H.264/AVC CAVLC (Context-based Adaptive Variable Length Coding) decoding which used for baseline profile and extended profile. Previous CAVLC architectures are consisted of five step block and each block gets effective bits from Controller block and Accumulator. If large number of non-zero coefficients exist, process for getting effective bits has to iterates many times. In order to reduce this unnecessary process, we propose two techniques, which combine five steps into four steps and reduce process to get efficiency bit by skipping addition step. By adopting these two techniques, the required processing time was reduced about 26% compared with previous architectures. It was designed in a hardware description language and total logic gate count was 16.83k using 0.18um standard cell library.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.6
• /
• pp.9-19
• /
• 1998

RAID technology that provides the disk I/O system with high performance and high availability is essential for OLTP server. This paper describes the design and implementation of the HIPSS RAID system that has been developed for the SPAX OLTP server. HIPSS has the following design objectives: high performance, high availability, standardization and modularization of external interface, and ease of maintenance. It guarantees high performance by providing 10 independent I/O channels, large data cache, and parity calculation engine. Hardware modularization of the host interface makes it easy to replace host interface hardware module. By providing dual power supply, dual array controller, and disk hot swapping, it provides the system with high availability Implementation of HIPSS and integration test on SPAX has been completed and performance measurement on HIPSS is now going on. In this paper, we provide the detail description for HIPSS system architecture and the implementation results.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.8 no.1
• /
• pp.170-178
• /
• 2004

In this work a high speed 8-error correcting Reed-Solomon decoder is designed using the modified Euclid algorithm. Decoding algorithm of Reed-Solomon codes consists of four steps, those are, compute syndromes, find error-location polynomials, decide error-locations, and determine error values. The decoding speed is increased and the latency is reduced by using the parallel architecture in the syndrome generator and a faster clock speed in the modified Euclid algorithm block. In addition. the error locator polynomial in Chien search block is separated into even and odd terms to increase the overall speed of the decoder. All the functionalities of the decoder are verified first through C++ programs. Verilog is used for hardware description, and then the decoder is synthesized with a $.25{\mu}m$ CMOS TML library. The functionalities of the chip is also verified through test vectors. The clock speed of the chip is 250MHz, and the maximum data rate is 1Gbps.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.36 no.1B
• /
• pp.71-79
• /
• 2011

This paper proposes a compiled-code simulator generation system based-on machine description language for efficient design space exploration in designing an embedded system optimized for a specific application. The proposed system generates a compiled-code simulator which maintains the functional accuracy of an event-driven simulator by determining instruction fetch and decoding processes statically. Generated simulator takes instruction-level and cycle-level simulation for estimating performances in embedded core. To show the efficiency of the constructed compiled-code simulator generator, architecture exploration had been performed for the JPEG encoder application. Starting with MIPS R3000 processor for one embedded core, the proposed system can produce the core showing optimized execution time for the application programming. In this process, a huge amount of simulation time has been used. Cycle-level compiled-code simulator has the functional accuracy and shows performance improvement by 21.7% in terms of simulation speed on the average when compared with an event-driven simulator.

• Journal of Information Science Theory and Practice
• /
• v.6 no.2
• /
• pp.46-61
• /
• 2018

The mobile social networking application Instagram is a well-known platform for sharing photos and videos. Since it is folksonomy-oriented, it provides the possibility for image indexing and knowledge representation through the assignment of hashtags to posted content. The purpose of this study is to analyze how Instagram users tag their pictures regarding different kinds of picture and hashtag categories. For such a content analysis, a distinction is made between Food, Pets, Selfies, Friends, Activity, Art, Fashion, Quotes (captioned photos), Landscape, and Architecture image categories as well as Content-relatedness (ofness, aboutness, and iconology), Emotiveness, Isness, Performativeness, Fakeness, "Insta"-Tags, and Sentences as hashtag categories. Altogether, 14,649 hashtags of 1,000 Instagram images were intellectually analyzed (100 pictures for each image category). Research questions are stated as follows: RQ1: Are there any differences in relative frequencies of hashtags in the picture categories? On average the number of hashtags per picture is 15. Lowest average values received the categories Selfie (average 10.9 tags per picture) and Friends (average 11.7 tags per picture); for highest, the categories Pet (average 18.6 tags), Fashion (average 17.6 tags), and Landscape (average 16.8 tags). RQ2: Given a picture category, what is the distribution of hashtag categories; and given a hashtag category, what is the distribution of picture categories? 60.20% of all hashtags were classified into the category Content-relatedness. Categories Emotiveness (about 4.38%) and Sentences (0.99%) were less often frequent. RQ3: Is there any association between image categories and hashtag categories? A statistically significant association between hashtag categories and image categories on Instagram exists, as a chi-square test of independence shows. This study enables a first broad overview on the tagging behavior of Instagram users and is not limited to a specific hashtag or picture motive, like previous studies.

• Archives of design research
• /
• v.4 no.1
• /
• pp.61-73
• /
• 1991

The exhibition activity that a company is rendering to their consumers for the purpose of advertisement, sales promotion and enhancement of company inage get more and more internationalized and specialized. A company is changing from mass production system to small quantity production of various kinds to meet consumer's individualization and differentiation. Also, a company is experiencing a major change in their marketing strategy. As the society is entering on Information Age, the contents that a company intends to give consumer may be different individually. If a consumer is informed wrong information of the goods, a company needs a place to meet consumer face to face where the consumer feels and understands the substance of the goods. This is the current characteristics of Exhibition Media. Based on the result of the current Special Exhibition home and abroad along with background and characteristics of special Exhibition, this study sets a following task reflecting the general trend of social, cultural and economic atmosphere. First, Current Exhibition Industry will be diversified into more Specialized Exhibition, while our Exhibition Industry is very shaky under severe international competition. Also, Exhibition Plan that involves with architecture, interior, graphic, industrial design and advertisement, etc., needs international competitiveness while enhancing identity of Exhibition Plan along with comprehensive marketing strategy in the future. Second, Among most of the local special Exhibitions which invite the general public are normally invited for company public relation contrary to those of U.S.A. and Europe. This signifies of our industrial and social structure's by-product. As the future exhibition become Information Com$$\mu$ication Exhibition which requires specialized technical explanation, the correct description of the goods should be set as a Judgement basis of Exhibition Plan. Third, In parallel with increase of the Exhibition, the equipment expenses of a company goes up continuously. In view of this, a study $$\mu$t be oriented for re-use and curtailment of expenditure of those equipment. Also, as the use of Assembly System B on the rise as a result of diversification of special Exhibition, a study on the development of new material & design for Exhibition Equipment only B required.

• Journal of KIISE:Computing Practices and Letters
• /
• v.7 no.2
• /
• pp.109-120
• /
• 2001

In this paper, we propose the design and implementation of a portable, extensible, and efficient performance visualization framework for high performance parallel program development. The framework adopts a layered architecture:consists of three independent layers instrumentation layer, trace interface layer and visualization layer. The instrumentation layer was constructed as an ECL which captures generated events, and the EDL/JPAL constitutes the trace interface layer to provide problem-oriented interfaces between visualization layer and instrumentation layer. Finally, the visualization layer was designed as plug-and-play style for easy elimination, addition and composition of various filters, views and view groups, The proposed performance visualization framework is expected to be used as an independent performance debugging and analysis tool and as a core component in an integrated parallel programming environment.

• The KIPS Transactions:PartD
• /
• v.15D no.4
• /
• pp.441-450
• /
• 2008

Recently, access control on form-based web information systems has become one of the useful methods for implementing client systems in a service-oriented architecture. In particular, XForms language is being adopted in many systems as a description language for XML-based user interfaces and server interactions. In this paper, we propose an efficient algorithm for the evaluation of XPath-based access rules for XForms pages. In this model, an XForms page is a sequence of queries and the client system performs user interface realization along with XPath rule evaluations. XPath rules have instance-dependent predicates, which for the most part are shared between rules. For the efficient evaluation of shared predicate expressions in access control rules, we proposed a predicate graph model that reuses the previously evaluated results for the same context node. This approach guarantees that each predicate expression is evaluated for the relevant xml node only once.

• Journal of Soil and Groundwater Environment
• /
• v.19 no.3
• /
• pp.111-122
• /
• 2014

Partitioning interwell tracer test (PITT) is a method to quantify and qualify a site contaminated with NAPLs (Non-Aqueous Phase Liquids). Analytical description of PITT assumes that the injection-pumping well pair is on the line of the ambient groundwater flow direction, but the test-well pair could frequently be off the line in a real field site, which could be an erroneous factor in analyzing PITT data. The purpose of this work is to study the influence of the angle of the test-well pair on the ambient groundwater flow direction based on the result from PITT. From the experiments, it was found that the obliqueness of the test-well pair to the ambient groundwater flow direction could affect the tracer test resulting in a decreased NAPL estimation efficiency. In case of an oblique arrangement of the test-well pair to the ambient flow direction, it was found that the injection of a chase fluid could enhance the estimation efficiency. An increase of the pumping rate could enhance the recovery rate but it cannot be said that a high pumping rate can increase the test efficiency because a high pumping rate cannot give partitioning tracers enough time to partition into NAPLs. The results have a implication that because the arrangement of the test-well pair is a controlling factor in performing and interpreting PITT in the field in addition to the known factors such as heterogeneity and the source zone architecture, flow direction should be seriously considered in arranging test-well pair.