• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.461-464
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• 1999

This study has been investigated that traps generated inside of the oxide and at the oxide interfaces by the stress bias voltage. The traps are charged near the cathode with negative charge and charged near the anode with positive charge. The charge state of the traps can easily be changed by application of low voltages after the stress high voltage. These trap generation involve either electron impact ionization processes or high field generation processes. It determined to the relative traps locations inside the oxides ranges from 113.4$\AA$ to 814$\AA$ with capacitor areas of 10$^{-3}$ $\textrm{cm}^2$ . The oxide charge state of traps generated by the stress high voltage contain either a positive or a negative charge.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.2
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• pp.17-24
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• 2000

In this paper, the stress and transient currents associated with the on and off time of applied voltage were used to measure the density and distribution of high voltage stress induced traps in thin silicon oxide films. The transient currents were due to the discharging of traps generated by high stress voltage in the silicon oxides. The trap distributions were relatively uniform new both cathode and anode interface. The trap densities were dependent on the stress polarity. The stress generated trap distributions were relatively uniform the order of 1011~1021[states/eV/cm2] after a stress voltage. It appear that the stress and transient current that flowed when the stress voltage were applied to the oxide was caused by carriers tunneling through the silicon oxide by the high voltage stress generated traps.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.1-8
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• 2004

Experimental results are presented for gate oxide degradation, such as SILC and soft breakdown, and its effect on device parameters under negative and positive bias stress conditions using n-MOSFET's with 3 nm gate oxide. The degradation mechanisms are highly dependent on stress conditions. For negative gate voltage, both interface and oxide bulk traps are found to dominate the reliability of gate oxide. However, for positive gate voltage, the degradation becomes dominated mainly by interface trap. It was also found the trap generation in the gate oxide film is related to the breakage of Si-H bonds through the deuterium anneal and additional hydrogen anneal experiments. Statistical parameter variations as well as the “OFF” leakage current depend on both electron- and hole-trapping. Our results therefore show that Si or O bond breakage by tunneling electron and hole can be another origin of the investigated gate oxide degradation. This plausible physical explanation is based on both Anode-Hole Injection and Hydrogen-Released model.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04b
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• pp.43-46
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• 2000

In this paper, the stress and transient currents associated with the on and off time of applied voltage were used to measure the density and distribution of high voltage stress induced traps in thin silicon oxide films. The transient currents were due to the discharging of traps generated by high stress voltage in the silicon oxides. The trap distributions were relatively uniform near both cathode and anode interface. The trap densities were dependent on the stress polarity. The stress generated trap distributions were relatively uniform the order of $10^{11}\sim10^{21}$[states/eV/$cm^2$] after a stress. The trap densities at the oxide silicon interface after high stress voltages were in the $10^{10}\sim10^{13}$[states/eV/$cm^2$]. It appear that the stress and transient current that flowed when the stress voltage were applied to the oxide was caused by carriers tunneling through the silicon oxide by the high voltage stress generated traps.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.10 no.6
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• pp.412-417
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• 2000

High electric field stressed trap distributions were investigated in the thin silicon oxide of polycrystalline silicon gate metal oxide semiconductor capacitors. The transient currents associated with the off time of stressed voltage were used to measure the density and distribution of high voltage stress induced traps. The transient currents were due to the discharging of traps generated by high stress voltage in the silicon oxides. The trap distributions were relatively uniform near both cathode and anode interface in polycrystalline silicon gate metal oxide semiconductor devices. The stress generated trap distributions were relatively uniform the order of $10^{11}$~$10^{12}$ [states/eV/$\textrm{cm}^2$] after a stress. The trap densities at the oxide silicon interface after high stress voltages were in the $10^{10}$~$10^{13}$ [states/eV/$\textrm{cm}^2$]. It was appeared that the transient current that flowed when the stress voltages were applied to the oxide was caused by carriers tunneling through the silicon oxide by the high voltage stress generated traps.

• Transactions of the Korean hydrogen and new energy society
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• v.27 no.2
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• pp.155-162
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• 2016

A proton exchange membrane fuel cell (PEMFC) produces only water at cathode by an electrochemical reaction between hydrogen and oxygen. The generated water is transported across the membrane from the cathode to the anode. The transported water collected in water-trap and drained to the cathode within the humidifier outlet. If the condensate water is not being drained at the appropriate time, condensate water in the anode can cause the performance degradation or fuel efficiency degradation of fuel cell by the anode flooding or unnecessary hydrogen discharge. In this study, we proposed an optimization method of condensate water drain logic for the water drain performance and the water drain algorithm as considered the condensate water generating speed prep emergency case. In conclusion, we developed the water management strategy of fuel processing system (FPS) as securing fuel efficiency and operating stability.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.17-20
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• 2002

This study has been investigated that traps generated inside of the oxide and at the oxide interfaces by the stress bias voltage. The traps are charged near the cathode with negative charge and charged near the anode with positive charge. The charge state of the traps can easily be changed by application of low voltages after the stress high voltage. These trap generation involve either electron impact ionization processes or high field generation processes. It determined to the relative traps locations inside the oxides ranges from 113.4A to 814A with capacitor areas of 10$^{-3}$ $\textrm{cm}^2$ The oxide charge state of traps generated by the stress high voltage contain either a positive or negative charge.

• 한국신재생에너지학회:학술대회논문집
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• 2008.05a
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• pp.57-60
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• 2008

KEPRI has studied planar type SOFC stacks using anode-supported single cells and kW class co-generation systems for residential power generation. A 1kW class SOFC system consisted of a hot box part, a cold BOP part and a water reservoir. A hot box part contains a SOFC stack made up of 48 single cells and ferritic stainless steel interconnectors, a fuel reformer, a catalytic combustor and heat exchangers. Thermal management and insulation system were especially designed for self-sustainable operation. A cold BOP part was composed of blowers, pumps, a water trap and system control units. When a 1kW class SOFC system was operated at $750^{\circ}C$ with hydrogen after pre-treatment process, the stack power was 1.2kW at 30 A and 1.6kW at 50A. Turning off an electric furnace, the SOFC system was operated using hydrogen and city gas without any external heat source. Under self-sustainable operation conditions, the stack power was about 1.3kW with hydrogen and 1.2kW with city gas respectively. The system also recuperated heat of about 1.1kW by making hot water.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.9 no.5
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• pp.521-526
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• 1999

It was investigated that traps were generated inside of the oxide and at the oxide interfaces by the stress bias voltage. The charge state of the traps can easily be changed by application of low voltage after the stress high voltage. It determined to the relative traps locations inside the oxides ranges from 113.4$\AA$to 814$\AA$ with capacitor areas of $10^{-3}{$\mid$textrm}{cm}^2$. The traps are charged near the cathode with negative charge and charged near the anode with positive charge. The oxide charge state of traps generated by the stress high voltage contain either a positive or a negative charge.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.1014-1018
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• 2007

We have demonstrated the enhancement of the power efficiency and device lifetime of organic light-emitting diodes (OLEDs) by introducing the ETL 1 / ETL2 (composite ETL) structure between EML and cathode and the HIL1 (composite HIL) / HIL2 between anode and HTL. Compared to reference devices retaining conventional architecture, novel OLED structure shows an outstanding EL efficiency that is 1.6 times higher (${\sim}4.5$ lm/w versus ${\sim}$ 2.71 lm/w for the reference device) and lower driving voltage $({\bigtriangleup}V>1V)$, but also a longer lifetime and smaller operating voltage drift over time. It is suggested in this work that the device performance can be improved by in-situ ohmic contact through novel electron controlled structure and reduction of charge accumulation in the interface through composite HIL