• 제목/요약/키워드: Analog pass

검색결과 103건 처리시간 0.026초

병렬 구조의 올패스 필터를 사용한 LPF에 관한 연구 (A Study on Low-Pass Filter using All-Pass Filter of Parallel Structure)

  • 김승영;김남호
    • 한국정보통신학회논문지
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    • 제5권3호
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    • pp.533-541
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    • 2001
  • 본 논문은 플랫트 딜레이 특성의 올패스 필터의 합을 이용한 로우패스 필터를 제시하였다. 이 필터는 병렬 구조의 올패스 필터로 구성하였고, 일반적인 아날로그 필터는 위상과 지연을 조정하는 것이 불가능하지만, 제시한 필터를 이용하면 위상과 지연을 조정하는 것이 용이하다는 장점을 가지고 있다. 그리고 통과대역 폭과 크기 특성, 군지연 특성과 차단 주파수를 비교 분석하였다. 아울러, 원하는 차단 주파수를 얻기 위해서 가중치를 인가하여, 융통성 있는 차단 주파수와 군지연 특성을 얻었다.

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2차 델타 시그마 변조기법을 이용한 고 정밀 및 고 안정 디지털 전자석 전원 장치에 관한 연구 (A Study on High Precision and High Stability Digital Magnet Power Supply Using Second Order Delta-Sigma modulation)

  • 김금수;장길진;김동희
    • 조명전기설비학회논문지
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    • 제29권3호
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    • pp.69-80
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    • 2015
  • This paper is writing about developing magnet power supply. It is very important for power supply to obtain output current in high precision and high stability. As a switching noise and a power noise are the cause of disrupting the stability of output current, to remove these at the front end, low pass filter with 300Hz cutoff frequency is designed and placed. And also to minimize switching noise of the current into magnet and to stop abrupt fluctuations, output filter should be designed, when doing this, we design it by considering load has high value inductance. As power supply demands the stability of less than 5ppm, high precision 24bit(300nV/bit) analog digital converter is needed. As resolving power of 24bit(300nV/bit) analog digital converter is high, it is also very important to design the input stage of analog digital converter. To remove input noise, 4th order low pass filter is composed. Due to the limitation of clock, to minimize quantization error between 15bit DPWM and output of ADC having 24bit resolving power, ${\Sigma}-{\Delta}$ modulation is used and bit contracted DPWM is constituted. And before implementing, to maximize efficiency, simulink is used.

블루투스 베이스밴드에 적용 가능한 디지털 로우패스 필터 (A Digital Low-pass Filter appliable for Bluetooth Baseband)

  • 문상국
    • 한국정보통신학회:학술대회논문집
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    • 한국해양정보통신학회 2005년도 추계종합학술대회
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    • pp.1000-1002
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    • 2005
  • 최대 7기기까지의 슬레이브 디바이스들과 연결이 가능한 블루투스 피코넷에서, RF 연결단으로 송신되는 무선 데이터는 블루투스 버전 1.1 송신 규약에 적합하도록 1마이크로미터 단위로 슬라이싱되어 베이스밴드 입력단으로 들어오게 된다. 본 연구에서는 상대적으로 불안정한 RF 디바이스에서 베이스밴드로 전달되는 아날로그 신호를 1 마이크로미터 단위의 정확한 슬라이싱을 가능하게 해 주고, 또한 불안정한 아날로그에 대한 신호의 노이즈를 제거할 수 있는 디지털 로우패스 필터를 설계하였다. 설계된 디지털 로우패스필터는 블루투스 RF 일체형 베이스밴드 침의 절전 모드, 정상동작 모드와 고속 동작 모드인 12MHz, 24MHz, 48MHz 각 주파수에서 모두 정상적으로 동작하였다.

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DRAM bus system을 위한 analog calibration 적용 Pre-emphasis Transmitter

  • 박정준;차수호;유창식;기중식
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2006년도 하계종합학술대회
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    • pp.653-654
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    • 2006
  • A Pre-emphasis transmitter for DRAM bus system has achieved 3.2Gbps/pin operation at 1.8V supply voltage with 0.18um CMOS process. The transmitter has 800MHz PLL to generate 4 phase clocks. The 4 phase clocks are used for input clock of PRBS and multiplexing. One tap pre-emphasis is used to reduce inter symbol interference (ISI) caused by channel low pass effects. The analog calibration makes the optimized driver impedance independent with the PVT variation.

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Field programmable analog arrays for implementation of generalized nth-order operational transconductance amplifier-C elliptic filters

  • Diab, Maha S.;Mahmoud, Soliman A.
    • ETRI Journal
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    • 제42권4호
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    • pp.534-548
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    • 2020
  • This study presents a new architecture for a field programmable analog array (FPAA) for use in low-frequency applications, and a generalized circuit realization method for the implementation of nth-order elliptic filters. The proposed designs of both the FPAA and elliptic filters are based on the operational transconductance amplifier (OTA) used in implementing OTA-C filters for biopotential signal processing. The proposed FPAA architecture has a flexible, expandable structure with direct connections between configurable analog blocks (CABs) that eliminates the use of switches. The generalized elliptic filter circuit realization provides a simplified, direct synthetic method for an OTA-C symmetric balanced structure for even/odd-nth-order low-pass filters (LPFs) and notch filters with minimum number of components, using grounded capacitors. The filters are mapped on the FPAA, and both architectures are validated with simulations in LTspice using 90-nm complementary metal-oxide semiconductor (CMOS) technology. Both proposed FPAA and filters generalized synthetic method achieve simple, flexible, low-power designs for implementation of biopotential signal processing systems.

Digital Filter Design using the Symbol Pulse Invariant Transformation

  • 김태수;;김형래
    • 한국통신학회논문지
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    • 제19권1호
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    • pp.1-9
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    • 1994
  • In general, when IIR digital filter are designed from analog filters, the bilinera transformation and the impluse invariant tramsformation are commonly used. It is known, however, that high frequency response of digital filters designed by these transformations can not be well approximated to the sampled analog signals. In this paper, the symbol pulse invariant transformation is analyzed theoretically so that the symbol pulse invariant transformation which was originally application to a rectangular pulse is newly applied to double rate pulse signals and generic shape pulse signals. Also, the relation of spectra between a transfer function of digital filter and one of analog filter is considered. Further, we apply to design the digital high pass filters using the symbol pulse invariant transformation method.

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체내 이식 신경 신호 기록 장치를 위한 저전압 저전력 아날로그 Front-End 집적회로 (A Low-Voltage Low-Power Analog Front-End IC for Neural Recording Implant Devices)

  • 차혁규
    • 전자공학회논문지
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    • 제53권10호
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    • pp.34-39
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    • 2016
  • 본 논문에서는 체내 이식용 신경 신호 기록 장치를 위한 저전압 저전력 아날로그 front-end 집적회로를 설계하였다. 제안된 집적 회로는 1 Hz에서 5 kHz 주파수 대역에 존재하는 신경 신호를 처리하기 위해 저잡음 neural 증폭기와 대역폭 조절이 가능한 능동 bandpass 필터로 구성되어 있다. Neural 증폭기는 우수한 잡음 특성을 위해 source-degenerated folded-cascode 연산증폭기를 기반으로 하여 설계하였고, 능동 필터의 경우 저전력의 current-mirror 연산증폭기를 이용하여 설계하였다. 능동 필터의 high-pass cutoff 주파수는 1 Hz에서 300 Hz까지 제어가 가능하며, low-pass cutoff 주파수는 300 Hz에서 8 kHz까지 제어가 가능하다. 전체 아날로그 front-end 회로는 53.1 dB의 전압 이득 성능과 1 Hz에서 10 kHz 대역에 대해서 $4.68{\mu}Vrms$의 입력 잡음 성능과 3.67의 noise efficiency factor 성능을 보인다. $18-{\mu}m$ CMOS 공정을 이용하여 설계를 하였고 1-V 전원에서 $3.2{\mu}W$의 전력 소모 성능을 갖는다. 칩 레이아웃 면적은 $0.19 mm^2$ 이다.

Design of Optimal Digital IIR Filters using the Genetic Algorithm

  • Jang, Jung-Doo;Kang, Seong G.
    • International Journal of Fuzzy Logic and Intelligent Systems
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    • 제2권2호
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    • pp.115-121
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    • 2002
  • This paper presents an evolutionary design of digital IIR filters using the genetic algorithm (GA) with modified genetic operators and real-valued encoding. Conventional digital IIR filter design methods involve algebraic transformations of the transfer function of an analog low-pass filter (LPF) that satisfies prescribed filter specifications. Other types of frequency-selective digital fillers as high-pass (HPF), band-pass (BPF), and band-stop (BSF) filters are obtained by appropriate transformations of a prototype low-pass filter. In the GA-based digital IIR filter design scheme, filter coefficients are represented as a set of real-valued genes in a chromosome. Each chromosome represents the structure and weights of an individual filter. GA directly finds the coefficients of the desired filter transfer function through genetic search fur given filter specifications of minimum filter order. Crossover and mutation operators are selected to ensure the stability of resulting IIR filters. Other types of filters can be found independently from the filter specifications, not from algebraic transformations.

디지털 셀룰라 시스템을 위한 개선된 GMSK 직교 변조기의 설계 (A design of an improved GMSK quadrature modulator for digital cellular system)

  • 송영준;한영열
    • 전자공학회논문지A
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    • 제33A권6호
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    • pp.32-41
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    • 1996
  • We propose the improved GMSK (gaussian-filtered minimum shift keying) quadrature modulator using the FIR(finite impulse response )filter whose coefficients are obtained form the differnce of phase response, and design its ASIC (applicaton specific integrated circuit) which can be used for GSM (global system for mobile communication) digital cellular system and DCS 1800 (digital cellular system at 1800MHz) personal communication system. Input data become quantized I and Q channel 10 bit signal through cosine and sine ROM mapping after being filtered by the FIR filter whose normalized bandwidth is 0.3 and designed by considering intersymbol interference as well as sampling ratio. These two signals become the GMSK modulated I and Q channel signal through DAC (digital-to-analog converter) and 7th order analog chebyshev LPF(low pass filter) respectively. The difference between the ideal analog signal and its digitized signal is analyzed in terms of sampling noise, quantization noise, truncation noise and coefficient noise. And the effect of the LPF following the DAC is considered. The ASIC design of the GMSK quadrature modulator is also confirmed by an experiment.

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CMOS 아날로그 집적회로를 위한 새로운 구조의 One port 저항 셀 (One port resistor cell for CMOS analog integrated circuits)

  • 조영창;김성환;최평
    • 전자공학회논문지A
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    • 제33A권3호
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    • pp.135-139
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    • 1996
  • It is difficult to fabricate precise resistors for the analog integrated circuits using MOS technology. Until now polysilicon resistors were used at the analog integrated circuits, but some deviations of resistance and sensitive variation processes still cause their misactions. In order to improve these misactions, we suggest a CMOS resistor cell which provides precise resistance and excellant linearity. Also we designed the second order active low pass filter using the CMOS resistor cells and verified their superior performances compared to the actual resistors.

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