• Journal of IKEEE
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• v.24 no.1
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• pp.364-367
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• 2020

This paper presents the off-grid PV-ESS system of sequential voltage control method applied to OR logic gate. The conventional off-grid PV-ESS system with the low-voltage series connection has problems due to capacity expansion. To solve these problems, this paper proposes a noble PV-ESS system with high efficiency and low cost by applying sequential voltage control technique of the high-voltage series connection of analog circuit type. The input voltage of DC to AC inverter can be converted from the low-voltage by the combinations of series connection of the conventional cascaded 24V solar cell unit modules to the high-voltage of 384V in battery. The output voltage of the battery was 384V as the each input voltage of three phase DC to AC inverter, and the each output voltage of three phase 10kW DC to AC inverter is designed to be AC380V@60Hz as the line to line rms voltage value. To prove the validity of the theoretical analysis by PSIM simulation, the operating characteristics of sequential voltage control system with OR logic gate were confirmed through experiment results.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.11 no.1
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• pp.114-122
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• 1997

This paper describes the design and development of a smart digital load cell used forweighing installations. Sice the load cell sensor to be used is very sensitive for weight cariation, the load cell must have the temperature stability, low-drift and the high-resolution of the A/D conversion for accuracy. A new analog circuit which is controlled by one chip micro-processer has been developed to reduce the offset voltage and the drift characteristics of operational amplifiers, and has been adapted into the digital load cell. Also, a software algorithm has been developed to obtain the stable and accurate A/D conversion. This software includes a RS-485 communication program to control the digital load cell, which gives a capability of backing-up the calibration data and transferring control data. The simulation and evaluation of the designed digital load cell has been shown as having the good performance. which will give useful application to the weighing installations as a remote weighing sensor.

• The Transactions of the Korea Information Processing Society
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• v.1 no.4
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• pp.469-478
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• 1994

In this paper, a high speed, high resolution information processing digital- analog converter was designed for high definition color graphic, digital image signal processing, HDTV. For high speed operation, matrix type current cell array, latch which is not use pipelined, and two dimensional structure decoder using transmission gate were designed. It is adopted to fast-conversion, low-power implementation and exhibited high performance at linearity and accuracy. To reduce silicon area and to maintain resolution, current cell array composed of weighted and non-weighted current cells. In this paper, deglitching current cell design for high accuracy, new switching algorithm assert to reduce switching error. It's This circuit dissipates 130W with a 5-V power supply, and operate above 100MHz with 10 bit resolution.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.3
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• pp.188-198
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• 2010

Recently, as the demand of the environmental-friendly energy storage system such as an electric double-layer condenser increases, that of the bidirectional charger/discharger for the systems also increases. However, when charging/discharging mode-change occurs, the charger/discharger employing a bi-directional DC-DC converter with a commercialized analog controller has a complex circuit scheme, and a poor transient response. On the other hand, if a single digital controller is used for the bi-directional mode, the system performances can be improved by application of an advanced power-processing algorithm. In the paper, an environmental-friendly power storage systems including an Electric Double Layer Capacitor(EDLC) banks were developed with a bi-directional buck-boost converter and a digital signal processor (TMS320F28335). A simulation test-bed was realized and tested by MATLAB Simulink, and the hardware experiment was performed which shows that the dynamic response was improved such as the simulation results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11A
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• pp.1812-1819
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• 2001

In this paper, it investigated the permitted limit of the analog nonideality for the SOSOC Σ-Δ modulator design which is satisfied with 1 [MHz] signal bandwidth and 12-bit resolution in the OSR=25. Firstly, it get the SOSOC Σ-Δ modulator model and gain coefficient which is suitable in low voltage for the Σ-Δ modulator design which is satisfied with the specification in the supply voltage 3.3 [Vl. And it provided the performance prediction of the Σ-Δ modulator and the permitted limit of the nonideality by adding the performance degradation facts of the Σ-Δ modulator such as the finite gain of the amplifier, the SR, the closed-loop pole, the switch ON resistance and the capacitor mismatch to the ideal Σ-Δ modulator model. When designed the Σ-Δ modulator which is satisfied with the specification by the base above, it will be able to predict the performance of the Σ-Δ modulator and the guide for the specification of the circuit which composes the Σ-Δ modulator.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.8
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• pp.610-618
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• 2017

This paper presents a 868/915 MHz CMOS RF transceiver for the ZigBee application. Using a switchless matching network, the off chip switch is removed to achieve the low cost RF transceiver, and by the elimination of the switch's insertion loss we can achieve the benefits for the RF receiver's noise figure and transmitter's power efficiency at the given output power. The receiver is composed of low-noise amplifier, mixer, and baseband analog(BBA) circuit. The transmitter is composed of BBA, mixer, and driver amplifier. And, the integer N type frequency synthesizer is designed. The proposed ZigBee RF full transceiver is implemented on the $0.18{\mu}m$ CMOS technology. Measurement results show that the maximum gain and the noise figure of the receiver are 97.6 dB and 6.8 dB, respectively. The receiver consumes 32 mA in the receiver mode and the transmitter 33 mA in the transmission mode.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.1A
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• pp.134-141
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• 2007

This paper presents a frequency synthesizer(FS) for 5.2GHz/2.4GHz dual band wireless applications which is designed in a standard $0.18{\mu}m$ CMOS1P6M process. The 2.4GHz frequency is obtained from the 5.2GHz output frequency of Voltage Controlled Oscillator (VCO) by using the Switched Capacitor (SC) and the divider-by-2. Power dissipations of the proposed FS and VCO are 25mW and 3.6mW, respectively. The tuning range of VCO is 700MHz and the locking time is $4{\mu}s$. The simulated phase noise of PLL is -101.36dBc/Hz at 200kHz offset frequency from 5.0GHz with SCA circuit on.

• Smart Media Journal
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• v.2 no.1
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• pp.27-30
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• 2013

In this paper, we research the hand tracking and calibration algorithm using the EPIC sensor. We analyze the characteristics of EPIC sensor to be more sensitive in the around E-filed, and then we implement the 2-dimensional axis-transformation using the difference of detected amplitude between EPIC sensors. In addition, we implement the calibration algorithm considering the characteristics of EPIC sensor, and then we apply the Kalman filter to efficiently track a target. Thus, we implement the environment of window applications for verification and analysis the implemented algorithm. In turn, we use the DAQ API to extract the analog data. The DAQ hardware has the function of measuring and generating an electrical signal. Moreover, we confirm the movement of mouse cursor by detecting the potential difference depending on the movement of the user's hands.

• Coupled systems mechanics
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• v.4 no.4
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• pp.279-295
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• 2015

The article presents a theoretical-experimental approach developed for modeling the coefficient of sliding friction in the dynamic system tool-workpiece in slide diamond burnishing of low-alloy unhardened steels. The experimental setup, implemented on conventional lathe, includes a specially designed device, with a straight cantilever beam as body. The beam is simultaneously loaded by bending (from transverse slide friction force) and compression (from longitudinal burnishing force), which is a reason for geometrical nonlinearity. A method, based on the idea of separation of the variables (time and metric) before establishing the differential equation of motion, has been applied for dynamic modeling of the beam elastic curve. Between the longitudinal (burnishing force) and transverse (slide friction force) forces exists a correlation defined by Coulomb's law of sliding friction. On this basis, an analytical relationship between the beam deflection and the sought friction coefficient has been obtained. In order to measure the deflection of the beam, strain gauges connected in a "full bridge" type of circuit are used. A flexible adhesive is selected, which provides an opportunity for dynamic measurements through the constructed measuring system. The signal is proportional to the beam deflection and is fed to the analog input of USB DAQ board, from where the signal enters in a purposely created virtual instrument which is developed by means of Labview. The basic characteristic of the virtual instrument is the ability to record and visualize in a real time the measured deflection. The signal sampling frequency is chosen in accordance with Nyquist-Shannon sampling theorem. In order to obtain a regression model of the friction coefficient with the participation of the diamond burnishing process parameters, an experimental design with 55 experimental points is synthesized. A regression analysis and analysis of variance have been carried out. The influence of the factors on the friction coefficient is established using sections of the hyper-surface of the friction coefficient model with the hyper-planes.

• Nuclear Engineering and Technology
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• v.53 no.10
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• pp.3406-3412
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• 2021

A real-time digital time-stamp sorting algorithm used in the In-Beam positron emission tomography (In-Beam PET) is presented. The algorithm is operated in the field programmable gate array (FPGA) and a small amount of registers, MUX and memory cells are used. It is developed for sorting the data of annihilation event from front-end circuits, so as to identify the coincidence events efficiently in a large amount of data. In the In-Beam PET, each annihilation event is detected by the detector array and digitized by the analog to digital converter (ADC) in Data Acquisition Unit (DAQU), with a resolution of 14 bits and sampling rate of 50 MS/s. Test and preliminary operation have been implemented, it can perform a sorting operation under the event count rate up to 1 MHz per channel, and support four channels in total, count rate up to 4 MHz. The performance of this algorithm has been verified by pulse generator and ²²Na radiation source, which can sort the events with chaotic order into chronological order completely. The application of this algorithm provides not only an efficient solution for selection of coincidence events, but also a design of electronic circuit with a small-scale structure.