• Title/Summary/Keyword: Analog circuit

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A 16-channel Neural Stimulator IC with DAC Sharing Scheme for Artificial Retinal Prostheses

  • Seok, Changho;Kim, Hyunho;Im, Seunghyun;Song, Haryong;Lim, Kyomook;Goo, Yong-Sook;Koo, Kyo-In;Cho, Dong-Il;Ko, Hyoungho
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.5
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    • pp.658-665
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    • 2014
  • The neural stimulators have been employed to the visual prostheses system based on the functional electrical stimulation (FES). Due to the size limitation of the implantable device, the smaller area of the unit current driver pixel is highly desired for higher resolution current stimulation system. This paper presents a 16-channel compact current-mode neural stimulator IC with digital to analog converter (DAC) sharing scheme for artificial retinal prostheses. The individual pixel circuits in the stimulator IC share a single 6 bit DAC using the sample-and-hold scheme. The DAC sharing scheme enables the simultaneous stimulation on multiple active pixels with a single DAC while maintaining small size and low power. The layout size of the stimulator circuit with the DAC sharing scheme is reduced to be 51.98 %, compared to the conventional scheme. The stimulator IC is designed using standard $0.18{\mu}m$ 1P6M process. The chip size except the I/O cells is $437{\mu}m{\times}501{\mu}m$.

Low Power 31.6 pJ/step Successive Approximation Direct Capacitance-to-Digital Converter (저전력 31.6 pJ/step 축차 근사형 용량-디지털 직접 변환 IC)

  • Ko, Youngwoon;Kim, Hyungsup;Moon, Youngjin;Lee, Byuncheol;Ko, Hyoungho
    • Journal of Sensor Science and Technology
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    • v.27 no.2
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    • pp.93-98
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    • 2018
  • In this paper, an energy-efficient 11.49-bit successive approximation register (SAR) capacitance-to-digital converter (CDC) for capacitive sensors with a figure of merit (FoM) of 31.6 pJ/conversion-step is presented. The CDC employs a SAR algorithm to obtain low power consumption and a simplified structure. The proposed circuit uses a capacitive sensing amplifier (CSA) and a dynamic latch comparator to achieve parasitic capacitance-insensitive operation. The CSA adopts a correlated double sampling (CDS) technique to reduce flicker (1/f) noise to achieve low-noise characteristics. The SAR algorithm is implemented in dual operating mode, using an 8-bit coarse programmable capacitor array in the capacitance-domain and an 8-bit R-2R digital-to-analog converter (DAC) in the charge-domain. The proposed CDC achieves a wide input capacitance range of 29.4 pF and a high resolution of 0.449 fF. The CDC is fabricated in a $0.18-{\mu}m$ 1P6M complementary metal-oxide-semiconductor (CMOS) process with an active area of 0.55 mm2. The total power consumption of the CDC is $86.4{\mu}W$ with a 1.8-V supply. The SAR CDC achieves a measured 11.49-bit resolution within a conversion time of 1.025 ms and an energy-efficiency FoM of 31.6 pJ/step.

The Calculation of Illuminance Distribution in Complex Interior using Montecarlo Simulation (몬테카를로 시뮬레이션을 이용한 다면 공간의 조도계산)

  • Kim, Hee-Chul;Chee, Chul-Kon;Kim, Hoon
    • The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.7 no.6
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    • pp.27-33
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    • 1993
  • In order to improve complicated construction and complex control which are didvantage of optimal PWM technique aimed at harmonic elimination method, this paper presented MRA(Mode1 Reference Adaptive) PWM technique that gating signal of inverter is generated by comparing the reference signal with the induced feedback signal at the reference model of load. Design of controller is composed of microprocessor and analog circuit. MRA PWM technique used in the paper is able to compensate the degradation of voltage efficiency to be generated by the ratio of the output voltage to the DC supply voltage being low for using conventional sinusoidal PWM technique. When the trapezoidal signal is employed as the reference signal. the low order harmonics of line current can be reduced and the switching pattern is made by on-line computation using comparatively simple numerical analysis.

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A Study on The MRA PWM Technique Using the Trapezoidal Waveform at Voltage Source Inverter(VSDI) (전압형 인버터(VSI)에서 사다리꼴파형을 이용한 MRA PWM 기법에 관한 연구)

  • 한완옥;원영진;이성백
    • The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.7 no.2
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    • pp.36-40
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    • 1993
  • In order to improve complicated construction and complex control which are disadvantage of optimal PWM technique aimed at harmonic elimination method, this paper presented MRA(Model Reference Adaptive) PWM technique that gatmg signal of inverter is generated by comparing the reference signal with the induced feedback signal at the reference model of load. Design of controller is composed of microprocessor and analog circuit. MRA PWM technique used in the paper is able to compensate the degradation of voltage efficiency to be generated by the ratio of the output voltage to the DC supply voltage being low for using conventional sinusoidal PWM technique. When the trapezoidal signal is employed as the reference signal. the low order harmonics of line current can be reduced and the switching pattern is made by on-line computation using comparatively simple numerical analysis.

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Implementation of Capacitance Measurement Equipment for Fault Diagnosis of Multi-channel Ultrasonic Probe (다중채널 초음파 프로브 고장진단을 위한 커패시턴스 측정 장치 구현)

  • Kang, Bub-Joo;Kim, Yang-soo
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.20 no.1
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    • pp.175-184
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    • 2016
  • In this paper, we propose the method to measure the capacitances using not LCR meter but capacitance to voltage(C/V) conversion. And we design the analog MUX circuits that convert 192 channels to 6 MUX channels in order to implement the diagnosis of multi-channel ultrasonic probe. This paper derives the conversion function that converts the digital voltage of each MUX channel to the capacitance using the least squares method because the circuit characteristics that convert the voltage of each MUX channel to the capacitance are different. The developed prototype illustrates the performance test results that the measure times are measured by within 4sec and the measure error rates of maximum, minimum, and average values are within 5% in terms of the repeated measurements of all 192 channels.

A Study on a Low Power Underwater Communication Modem for Implementation of Underwater Sensor Networks (수중 센서 네트워크를 위한 저전력 수중 통신 모뎀 연구)

  • Choi, Yong-Woo;Hwang, Jun Hyeok;Park, Dong Chan;Kim, Suk Chan
    • Journal of Advanced Marine Engineering and Technology
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    • v.39 no.3
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    • pp.268-273
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    • 2015
  • Recently many countries are researching actively underwater sensor networks for securing ocean resources and changes of ocean environment in all over the world. Current the commercial modem are not suitable because it has characteristics of long distance, higher price, larger power consumption with the special object mainly. In this paper, a low power and compact underwater communication modem which is suitable for underwater sensor networks is implemented. It is comprised by using a simple analog circuit for non-coherent BFSK modulation method, ultra low power MCU and orthogonal codes with a less operation and a simple implementation. It was experimented an underwater communication using our modem in a water tank and open sea farms. It communicates fewer than $10^{-4}$ bit error rate.

Deign of Small-Area Dual-Port eFuse OTP Memory IP for Power ICs (PMIC용 저면적 Dual Port eFuse OTP 메모리 IP 설계)

  • Park, Heon;Lee, Seung-Hoon;Park, Mu-Hun;Ha, Pan-Bong;Kim, Young-Hee
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.8 no.4
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    • pp.310-318
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    • 2015
  • In this paper, dual-port eFuse OTP (one-time programmable) memory cells with smaller cell sizes are used, a single VREF (reference voltage) is used in the designed eFuse OTP IP (intellectual property), and a BL (bit-line) sensing circuit using a S/A (sense amplifier) based D F/F is proposed. With this proposed sensing technique, the read current can be reduced to 3.887mA from 6.399mA. In addition, the sensing resistances of a programmed eFuse cell in the program-verify-read and read mode are also reduced to $9k{\Omega}$ and $5k{\Omega}$ due to the analog sensing. The layout size of the designed 32-bit eFuse OTP memory is $187.845{\mu}m{\times}113.180{\mu}m$ ($=0.0213{\mu}m2$), which is confirmed to be a small-area implementation.

Development of Unmanned Speed Sprayer(I) -Remote Control and Induction Cable System- (무인 스피드 스프레이어의 개발(I) -원격제어 및 유도케이블 시스템-)

  • 장익주;김태한;조명동
    • Journal of Biosystems Engineering
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    • v.20 no.3
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    • pp.226-235
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    • 1995
  • An unmanned speed sprayer was developed using a remote control and an inductive cable guidance systems to protect operators and environment from hazardous pesticides. The sprayer consists of a remote control system, an induction system, obstacle detectors, control actuators and an one-chip microcomputer. The sprayer can be operated by the induction guidance and/or remote control. The following summarize characteristics of the developed speed sprayer. 1) Both the remote control and the induction guidance operation were possible with the developed speed sprayer. 2) Sixteen functions of the forwarding, backing, halting, steering, 3-way valve for nozzles and fan operating etc. were utilized on the remote control system. 3) It was concluded that the DTMF method, having less transmitting error, performed better than the FSK method for an agricultural remote controller. A radio station may be necessary. 4) The digital inductive guidance system, consisting of five low-impedance detection coils and a window comparator circuit, performed better than the analog detecting system, guiding route using inductive voltage differential from tow detection coils.

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Embodiment of living body measure system modeling for Rehalibitation treatment of positive simulation for HRV algorithm analysis interface of Mobile base (모바일 기반의 HRV 알고리즘 분석 인터페이스에 대한 실증적 시뮬레이션의 재활치료용 생체계측 시스템 모델링의 구현)

  • Kim, Whi-Young
    • Journal of the Korea Computer Industry Society
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    • v.7 no.4
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    • pp.437-446
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    • 2006
  • Mobilecomputer offers more fundamental role than role assistance enemy of modern technology equipment and new Information <중략> These main weakness puts in structural relation between elements that compose system. Therefore, dynamics research that time urea of systematic adjustment has selected method code Tuesday nerve dynamics enemy who groping of approach that become analysis point is proper and do with recycling bioelectricity signal. Nature model of do living body signal digital analysis chapter as research result could be developed and scientific foundation groping could apply HSS (Hardware-software system) by rehalibitation purpose. Special quality that is done radish form Tuesday of bioelectricity signal formation furthermore studied, and by the result, fundamental process of bodysignal in do structure circuit form of analog - digital water supply height modelling do can.

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Digital Control for BUCK-BOOST Type Solar Array Regulator (벅-부스트 형 태양전력 조절기의 디지털 제어)

  • Yang, JeongHwan;Yun, SeokTeak;Park, SeongWoo
    • Journal of Satellite, Information and Communications
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    • v.7 no.3
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    • pp.135-139
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    • 2012
  • A digital controller can simply realize a complex operation algorithm and power control process which can not be applied by an analog circuit for a solar array regulator(SAR). The digital resistive control(DRC) makes an equivalent input impedance of the SAR be resistive characteristic. The resistance of the solar array varies largely in a voltage source region and slightly in a current source region. Therefore when the solar array regulator is controlled by the DRC, the Advanced Incremental Conductance MPPT Algorithm with a Variable Step Size(AIC-MPPT-VSS) is suitable. The AIC-MPPT-VSS, however, using small signal resistance and large signal resistance of the solar array can not limit the absolute value of the solar array power. In this paper, the solar array power limiter is suggested and the BUCK-BOOST type SAR which is fully controlled by the digital controller is verified by simulation.