• Journal of the Korean Institute of Telematics and Electronics
• /
• v.27 no.8
• /
• pp.1255-1259
• /
• 1990

A new ripple analog-to-digital converter (ADC) has been developed. It consists of two parallel ADCs and a switching network. The circuit operates on the analog input signal in two serial steps. First, a coarse conversion is made to determine the most significant bits by the first parallel ADC. The resultant bits control the switching network to connect a series resistor segment, within which the analog signal is contained, to the second parallel ADC. At second step, a fine conversion is made to determine the least significant bits by the second parallel ADC. The circuit requires 2(2\ulcorner\ulcorner1) comparators, 2(2\ulcorner\ulcorner resistors, and 2(2\ulcorner\ulcorner swithches for N-bit resolution.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.47 no.3
• /
• pp.13-18
• /
• 2010

This work proposes and characterizes switched-capacitor type cyclic digital-to-analog converter for display data driving. The proposed digital-to-analog converter composes simple structure, and can be implemented for low-power, small area display driver ICs. By circuit level simulations, it is verified that the op-amp input referred offset is attenuated at the DAC output and the circuit performance is robust at 0.5% of capacitor mismatch.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.13 no.6
• /
• pp.647-654
• /
• 2013

The design and analysis of analog circuit application on CMOS technology are a challenge in deep sub-micrometer process. This paper is a study on the performance value of Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with Gate Stack and the channel engineering Single Halo (SH), Double Halo (DH). Four different structures have been analysed keeping channel length constant. The short channel parameters and different sub-threshold analog figures of merit (FOMs) are analysed. This work extensively provides the device structures which may be applicable for high speed switching and low power consumption application.

• Journal of information and communication convergence engineering
• /
• v.8 no.4
• /
• pp.461-465
• /
• 2010

This paper describes the design method of Time-to-Digital Converter(TDC) to obtain the constant delay time and good reliability. The reliability property is described with delay elements. In TDC the time signal is converted to digital value which is based on delay elements for the time interpolation. To obtain the constant delay time, the first and the last delay elements have different structure compared to the middle delay elements. In the first and the last delay elements, the driving ability could be controlled for the different delay time. The delay element can be designed by analog and digital devices. The delay time of the element using analog devices is not sensitive to process parameters than that of the element using digital devices. And the TDC circuit by the elements using analog devices shows better reliability than that by the elements using digital devices also.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.8 no.1
• /
• pp.105-111
• /
• 2013

We have developed an analog associative memory implemented with an analog array which has linear writing and erasing characteristics. The associative memory adopts a winner-take-all strategy. The operation for reading in the memory is executed with an absolute differencing circuit and a winner-take-all (WTA) circuit suitable for a nearest-match function of a content-addressable memory. We also present a system architecture that enables highly-paralleled fast writing and quick readout as well as high integration density. A multiple memory cell configuration is also presented for achieving higher integration density, quick readout, and fast writing. The system technology presented here is ideal for a real time recognition system. We simulate the function of the mechanism by menas of Hspice with $1.2{\mu}$ double poly CMOS parameters of MOSIS fabrication process.

• Journal of Drive and Control
• /
• v.9 no.4
• /
• pp.58-61
• /
• 2012

The customers who used the hydroulic system desire the product that has more detailed specification quickly during the industrial technology is developed. Every researcher try to reduce the developed period and to satisfy the customers' desire. Lot's of simulation software and hardware already was used to be satisfied those purpose. But these kind of equipment need a lot of cost to set up and technical knowledge to drive that system. This paper concerns about analog PID controller that can be assembled with a few resistor, condenser and optional amplifier and doesn't need technical knowledge to drive. At the first, the plant was modeled mathematically to design the analog PID controller's circuit. After that, PID controller's parameter was selected by customers' desire. Finally, the analog PID controller's circuit was assembled from the control law. The circuit's availability was confirmed by step response test in the controlled system.

• Journal of Multimedia Information System
• /
• v.8 no.2
• /
• pp.143-146
• /
• 2021

This work presents an automated transistor biasing scheme for analog integrated circuits. In order to effectively bias the transistor at a desired operating point, the proposed method uses a linearized transistor circuit model along with the curve fitted expressions obtained from the pre-simulated I-V characteristics of the actual transistor. As a result, the transistor size that leads to the desired operating point can be easily determined without heavily relying on the circuit simulator, which will lead to significant design time reduction. Furthermore, the proposed method is applied to an actual amplifier circuit where the design time based on the proposed biasing method showed 10× faster than the conventional design approach using the circuit simulator.

• Transactions on Electrical and Electronic Materials
• /
• v.11 no.1
• /
• pp.20-23
• /
• 2010

The analog front end (AFE) of a radio frequency identification transponder using the ISO 14443 type A standard with a 100% amplitude shift keying (ASK) modulation is proposed in this paper and verified by circuit simulations and measurements. This AFE circuit, using a 13.56 MHz carrier frequency, consists of a rectifier, a modulator, a demodulator, a regulator, a power on reset, and a dynamically enabled digital phase locked loop (DPLL). The DPLL, with a charge pump enable circuit, was used to recover the clock of a 100% modulated ASK signal during the pause period. A high voltage lateral double diffused metal-oxide semiconductor transistor was used to protect the rectifier and the clock recovery circuit from high voltages. The proposed AFE was fabricated using the $0.18\;{\mu}m$ standard CMOS process, with an AFE core size of $350\;{\mu}m\;{\times}\;230\;{\mu}m$. The measurement results show that the DPLL, using a demodulator output signal, generates a constant 1.695 MHz clock during the pause period of the 100% ASK signal.

• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.1019-1022
• /
• 2003

This paper has proposed a 4- bit 20MHz Flash A/D converter design available analog signal processing and realized its intergrated circuit. The parallel comparison method A/D converter quantized analog signals swiftly using various converters. Also this theme has designed economic power dissipation circuit using a preamplifier of low volt & power CMOS comparator. Also the system was fabricated by Hynix 0.35um CMOS process.

• Proceedings of the Korean Society of Marine Engineers Conference
• /
• 2005.11a
• /
• pp.204-205
• /
• 2005

The following instructions give you basic guidelines for preparing camera-ready papers for the proceeding of the KOSME. We recommend you to use the HWP word processor.