JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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A Study of SCEs and Analog FOMs in GS-DG-MOSFET with Lateral Asymmetric Channel Doping

  • Sahu, P.K. (Department of Electricl Engineering, National Institute of Technology) ;
  • Mohapatra, S.K. (Department of Electricl Engineering, National Institute of Technology) ;
  • Pradhan, K.P. (Department of Electricl Engineering, National Institute of Technology)
  • Received : 2013.05.24
  • Accepted : 2013.08.15
  • Published : 2013.12.31
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Abstract

The design and analysis of analog circuit application on CMOS technology are a challenge in deep sub-micrometer process. This paper is a study on the performance value of Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with Gate Stack and the channel engineering Single Halo (SH), Double Halo (DH). Four different structures have been analysed keeping channel length constant. The short channel parameters and different sub-threshold analog figures of merit (FOMs) are analysed. This work extensively provides the device structures which may be applicable for high speed switching and low power consumption application.

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References

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