• Journal of Biosystems Engineering
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• v.20 no.3
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• pp.226-235
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• 1995

An unmanned speed sprayer was developed using a remote control and an inductive cable guidance systems to protect operators and environment from hazardous pesticides. The sprayer consists of a remote control system, an induction system, obstacle detectors, control actuators and an one-chip microcomputer. The sprayer can be operated by the induction guidance and/or remote control. The following summarize characteristics of the developed speed sprayer. 1) Both the remote control and the induction guidance operation were possible with the developed speed sprayer. 2) Sixteen functions of the forwarding, backing, halting, steering, 3-way valve for nozzles and fan operating etc. were utilized on the remote control system. 3) It was concluded that the DTMF method, having less transmitting error, performed better than the FSK method for an agricultural remote controller. A radio station may be necessary. 4) The digital inductive guidance system, consisting of five low-impedance detection coils and a window comparator circuit, performed better than the analog detecting system, guiding route using inductive voltage differential from tow detection coils.

• Journal of Advanced Marine Engineering and Technology
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• v.17 no.5
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• pp.71-85
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• 1993

The Cycloconverter that the author is going to treat in this paper, has strong advantages over the D.C. Link Inverter in points of chattering torque problem and natural commutation. Thus, the Cycloconverter is expected to be well applied to large and low-speed machines which require better speed control at low frequency. But the control circuit of Cycloconverter has two weak points described as follows. 1) Because of its rather complicated control circuit, it is likely to be illoperating due to unexpected noise signals, thus the higher the accuracy and reliability of the circuit is required to be, the more the circuit may cost. 2) Because the load current is not purely sinusoidal, the Cycloconverter may possibly be destroyed in case of inaccurate convert switching resulted from the difficulties in detecting the load current-zero and the current direction at the moment. In this paper, the author first of all intends to design and build a modified VVVF-type Noncirculating Current Cycloconverter to which recently proposed control methods are applied for improving the circuit simplicity, the control performance, and the system reliability. And then, experiments for observing the output waveforms of the Cycloconverter which is controlled by Singled-Board Computer using 8086 16-bit microprocesser are carried out. Finally the author concludes the result of this study as follows. 1) By replacing the conventional analog control circuits such as Reference Wave Generator, Cosine Timing Wave Generator, and Comparator with softwares, a great circuit simplicity is achieved. 2) The output of the designed Cycloconverter changes its frequency very fast without showing discontinuity of its waveform, and this waveform characteristics enables the smooth speed control of Induction Motor. 3) The design control circuit of Cycloconverter can be applied to the systems of 12 or 24 pulses because of its short processing period.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.1
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• pp.63-70
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• 2015

In this paper, a receiver has been developed in a $0.11-{\mu}m$ CMOS technology for 900 MHz RFID communication system applications. The receiver is composed of an envelope detector, a low-pass-filter, a comparator, D flip-flops, as well as an oscillator to provide the clock for digital blocks. The receiver is designed for low power consumption, which would be suitable for passive RFID tags. In this circuit, a digital data slicer was employed instead of the conventional analog data slicer in order to reduce the power consumption. The clock frequency is 1.68 MHz and the circuit operates with a power consumption as small as $5{\mu}W$. The chip size is $325{\mu}m{\times}290{\mu}m$ excluding the probing pads.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.98-107
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• 2013

This work describes a 13b 100 MS/s 0.13 um CMOS four-stage pipeline ADC for 3G communication systems. The proposed SHA-free ADC employs a range-scaling technique based on switched-capacitor circuits to properly handle a wide input range of $2V_{P-P}$ using a single on-chip reference of $1V_{P-P}$. The proposed range scaling makes the reference buffers keep a sufficient voltage headroom and doubles the offset tolerance of a latched comparator in the flash ADC1 with a doubled input range. A two-step reference selection technique in the back-end 5b flash ADC reduces both power dissipation and chip area by 50%. The prototype ADC in a 0.13 um CMOS demonstrates the measured differential and integral nonlinearities within 0.57 LSB and 0.99 LSB, respectively. The ADC shows a maximum signal-to-noise-and-distortion ratio of 64.6 dB and a maximum spurious-free dynamic range of 74.0 dB at 100 MS/s, respectively. The ADC with an active die area of 1.2 $mm^2$ consumes 145.6 mW including high-speed reference buffers and 91 mW excluding buffers at 100 MS/s and a 1.3 V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.3
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• pp.1-8
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• 2000

This paper presents a simulation model of the Quadrature detector to demodulate FSK signal, which is widely used in wireless paging system for its simple hardware implementation and economics of It fabrication. Quadrature detecter has nonlinear phase characteristic for changes linear changes of input signal frequency. So until now Quadrature detector system analysis remained a difficult problem and performance analysis has not been carried out adequately On these backgrounds, this paper presents the FSK signal demodulation process using Quadrature detector and optimal performance derived from digital simulation technique. First, PSN(Phase Shift Network) which is composed of analog RLC tank circuit is transformed into its equivalent digital transfer function using First-order-hold theorem. Though the demodulated outputs of the Quadrature detector for 4FSK are 4-level signals, only 2 comparators are used and it is shown that optimal performance can be obtained by choosing operation parameter Q value and threshold level decision which are proposed herein.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.4
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• pp.303-309
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• 2013

A low power 6-bit flash ADC that uses an input voltage range detection algorithm is described. An input voltage level detector circuit has been designed to overcome the disadvantages of the flash ADC which consume most of the dynamic power dissipation due to comparators array. In this work, four digital input voltage range detectors are employed and each input voltage range detector generates the specific clock signal only if the input voltage falls between two adjacent reference voltages applied to the detector. The specific clock signal generated by the detector is applied to turn the corresponding latched comparators on and the rest of the comparators off. This ADC consumes 68.82mW with a single power supply of 1.2V and achieves 4.9 effective number of bits for input frequency up to 1MHz at 500 MS/s. Therefore it results in 4.75pJ/step of Figure of Merit (FoM). The chip is fabricated in 0.13-um CMOS process.

• 전자공학회논문지 IE
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• v.46 no.4
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• pp.1-7
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• 2009

The final goal of ITS and ETC will be to improve the traffic efficiency and mobile safety without new road construction. DSRC system is emerging nowadays as a solution of them. China DSRC standard which was released in May 2007 has low bit rate, short message and simple MAC control. The DSRC system users want a long lifetime over 1 year with just one battery. In this paper, we propose the SoC of very low power consumption architecture. Several digital logic concept and analog power control logics were used for very low power consumption. The SoC operation mode and clock speed, operation voltage range, wakeup signal detector, analog comparator and Internal Voltage Regulator & External Power Switch were designed. We confirmed that the SoC power consumption is under 8.5mA@20Mhz, 0.9mA@1Mhz in active mode, and under 5uA in power down mode, by computer simulation. The design of SoC was finished on Aug. 2008, and fabricated on Nov. 2008 with $0.18{\mu}m$ CMOS process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.5
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• pp.25-33
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• 2011

This work proposes a skinny-type 10b 50MS/s 0.13um CMOS three-step pipeline ADC for CIS applications. Analog circuits for CIS applications commonly employ a high supply voltage to acquire a sufficiently acceptable dynamic range, while digital circuits use a low supply voltage to minimize power consumption. The proposed ADC converts analog signals in a wide-swing range to low voltage-based digital data using both of the two supply voltages. An op-amp sharing technique employed in residue amplifiers properly controls currents depending on the amplification mode of each pipeline stage, optimizes the performance of op-amps, and improves the power efficiency. In three FLASH ADCs, the number of input stages are reduced in half by the interpolation technique while each comparator consists of only a latch with low kick-back noise based on pull-down switches to separate the input nodes and output nodes. Reference circuits achieve a required settling time only with on-chip low-power drivers and digital correction logic has two kinds of level shifter depending on signal-voltage levels to be processed. The prototype ADC in a 0.13um CMOS to support 0.35um thick-gate-oxide transistors demonstrates the measured DNL and INL within 0.42LSB and 1.19LSB, respectively. The ADC shows a maximum SNDR of 55.4dB and a maximum SFDR of 68.7dB at 50MS/s, respectively. The ADC with an active die area of 0.53$mm^2$ consumes 15.6mW at 50MS/s with an analog voltage of 2.0V and two digital voltages of 2.8V ($=D_H$) and 1.2V ($=D_L$).

• Journal of Preventive Medicine and Public Health
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• v.37 no.4
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• pp.381-389
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• 2004

Objective : To compare the efficacy between SKI306X and Diclofenac by using generalized estimating equations (GEE) methodology in the analysis of correlated bivariate binary outcome data in Osteoarthritis (OA) diseases. Methods : A randomized, double-blind, active comparator-controlled, non-inferiority clinical trial was conducted at 5 institutions in Korea with the random assignment of 248 patients aged 35 to 75 years old with OA of the knee and clinical evidence of OA. Patients were enrolled in this study if they had at least moderate pain in the affected knee joint and a score larger than 35mm as assessed by VAS (Visual Analog Scale). The main exposure variable was treatment (SKI 306X vs. Diclofenac) and other covariates were age, sex, BMI, baseline VAS, center, operation history (Yes/No), NSAIDS (Y/N), acupuncture (Y/N), herbal medicine (Y/N), past history of musculoskeletal disease (Y/N), and previous therapy related with OA (Y/N). The main study outcome was the change of VAS pain scores from baseline to the 2nd and 4th weeks after treatment. Pain scores were obtained as baseline, 2nd and 4th weeks after treatment. We applied GEE approach with empirical covariance matrix and independent(or exchangeable) working correlation matrix to evaluate the relation of several risk factors to the change of VAS pain scores with correlated binary bivariate outcomes. Results : While baseline VAS, age, and acupuncture variables had protective effects for reducing the OA pain, its treatment (Joins/Diclofenac) was not statistically significant through GEE methodology (ITT:aOR=1.37, 95% CI=(0.8200, 2.26), PP:aOR=1.47, 95% CI=(0.73, 2.95)). The goodness-of-fit statistic for GEE (6.55, p=0.68) was computed to assess the adequacy of the fitted final model. Conclusions : Both ANCOVA and GEE methods yielded non statistical significance in the evaluation of non-inferiority of the efficacy between SKI306X and Diclofenac. While VAS outcome for each visit was applied in GEE, only VAS outcome for the fourth visit was applied in ANCOVA. So the GEE methodology is more accurate for the analysis of correlated outcomes.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.3
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• pp.184-196
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• 2020

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for precision measurement of current flowing through a secondary cell battery in a battery management system (BMS). The proposed modulator implements two switched capacitor integrators and a single-bit comparator with peripheral circuits such as a non-overlapping clock generator and a bias circuit. The proposed structure is designed to be applied to low-side current sensing method with low common mode input voltage. Using the low-side current measurement method has the advantage of reducing the burden on the circuit design. In addition, the ±30mV input voltage is resolved by the ADC with 15-bit resolution, eliminating the need for an additional programmable gain amplifier (PGA). The proposed a single-bit 2nd-order delta-sigma modulator has been implemented in a 350-nm CMOS process. It achieves 95.46-dB signal-to-noise-and-distortion ratio (SNDR), 96.01-dB spurious-free dynamic range (SFDR), and 15.56-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 400 for 5-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 670×490 ㎛2 and 414 ㎼, respectively.