• Title/Summary/Keyword: Analog CMOS

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Design and Implementation of Circuit Analyzer for Electronics Appliance Troubleshooting and Diagnosis using Curve Tracer Technology (파형추적기술을 이용한 전자기기 고장진단용 회로분석기 설계 및 구현)

  • 장재철;양규식
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.3 no.2
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    • pp.273-280
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    • 1999
  • This paper presents the design and implementation of circuit analyzer system for the convenient troubleshooting and diagnosis of the electronics appliance using the curve tracer technology of analog signature analysis. The circuit analyzer provides advanced troubleshooting capabilities to simplify testing newer technology components such as CMOS and MOS circuits, its built-in pulse generator lets thoroughly troubleshoot gate-fired devices such as SCRs, TRIACs and optocouplers. The circuit analyzer while the power to the circuitry testing is turned of, so that avoid an accidental short that could cause further damage, its allow to analyze the impedance state of a solid-state component, which makes it perfect for finding leakage or substrate damage that has brought a system or PCB down prematurely. Because it can compare suspect components to known-good equivalents, it's verified the ideal application for troubleshooting when documentation is missing or incomplete.

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Design of single-chip NFC transceiver (단일 칩 NFC 트랜시버의 설계)

  • Cho, Jung-Hyun;Kim, Shi-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.1
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    • pp.68-75
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    • 2007
  • A single chip NFC transceiver supporting not only NFC active and passive mode but also 13.56MHz RFID reader and tag mode was designed and fabricated. The proposed NFC transceiver can operate as a RFID tag even without external power supply which has dual antenna structure for initiator and target. The area increment due to additional target antenna is negligible because the target antenna is constructed by using a shielding layer of initiator antenna. The analog front end circuit of the proposed NFC transceiver consists of a transmitter and receiver of reader/writer block supporting NFC initiator or RFID reader mode, and a tag circuit for target of passive NFC mode or RFID tag mode. The maximum baud rate of the proposed NFC device is 212kbps by using UART serial interface. The chip has been designed and fabricated using a Magnachip's $0.35{\mu}m$ double poly 4-metal CMOS process, and the effective area of the chip is 2200um by 3600um.

A 12b 100 MS/s Three-Step Hybrid Pipeline ADC Based on Time-Interleaved SAR ADCs

  • Park, Jun-Sang;An, Tai-Ji;Cho, Suk-Hee;Kim, Yong-Min;Ahn, Gil-Cho;Roh, Ji-Hyun;Lee, Mun-Kyo;Nah, Sun-Phil;Lee, Seung-Hoon
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.2
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    • pp.189-197
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    • 2014
  • This work proposes a 12b 100 MS/s $0.11{\mu}m$ CMOS three-step hybrid pipeline ADC for high-speed communication and mobile display systems requiring high resolution, low power, and small size. The first stage based on time-interleaved dual-channel SAR ADCs properly handles the Nyquist-rate input without a dedicated SHA. An input sampling clock for each SAR ADC is synchronized to a reference clock to minimize a sampling-time mismatch between the channels. Only one residue amplifier is employed and shared in the proposed ADC for the first-stage SAR ADCs as well as the MDAC of back-end pipeline stages. The shared amplifier, in particular, reduces performance degradation caused by offset and gain mismatches between two channels of the SAR ADCs. Two separate reference voltages relieve a reference disturbance due to the different operating frequencies of the front-end SAR ADCs and the back-end pipeline stages. The prototype ADC in a $0.11{\mu}m$ CMOS shows the measured DNL and INL within 0.38 LSB and 1.21 LSB, respectively. The ADC occupies an active die area of $1.34mm^2$ and consumes 25.3 mW with a maximum SNDR and SFDR of 60.2 dB and 69.5 dB, respectively, at 1.1 V and 100 MS/s.

An Offset and Deadzone-Free Constant-Resolution Phase-to-Digital Converter for All-Digital PLLs (올-디지털 위상 고정 루프용 오프셋 및 데드존이 없고 해상도가 일정한 위상-디지털 변환기)

  • Choi, Kwang-Chun;Kim, Min-Hyeong;Choi, Woo-Young
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.2
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    • pp.122-133
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    • 2013
  • An arbiter-based simple phase decision circuit (PDC) optimized for high-resolution phase-to-digital converter made up of an analog phase-frequency detector and a time-to-digital converter for all-digital phase-locked loops is proposed. It can distinguish very small phase difference between two pulses even though it consumes lower power and has smaller input-to-output delay than the previously reported PDC. Proposed PDC is realized using 130-nm CMOS process and demonstrated by transistor-level simulations. A 5-bit P2D having no offset nor deadzone using the PDC is also demonstrated. A harmonic-lock-free and small-phase-offset delay-locked loop for fixing the P2D resolution regardless of PVT variations is also proposed and demonstrated.

3-D Hetero-Integration Technologies for Multifunctional Convergence Systems

  • Lee, Kang-Wook
    • Journal of the Microelectronics and Packaging Society
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    • v.22 no.2
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    • pp.11-19
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    • 2015
  • Since CMOS device scaling has stalled, three-dimensional (3-D) integration allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. 3-D integration has many benefits such as increased multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, because it vertically stacks multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip. Anticipated applications start with memory, handheld devices, and high-performance computers and especially extend to multifunctional convengence systems such as cloud networking for internet of things, exascale computing for big data server, electrical vehicle system for future automotive, radioactivity safety system, energy harvesting system and, wireless implantable medical system by flexible heterogeneous integrations involving CMOS, MEMS, sensors and photonic circuits. However, heterogeneous integration of different functional devices has many technical challenges owing to various types of size, thickness, and substrate of different functional devices, because they were fabricated by different technologies. This paper describes new 3-D heterogeneous integration technologies of chip self-assembling stacking and 3-D heterogeneous opto-electronics integration, backside TSV fabrication developed by Tohoku University for multifunctional convergence systems. The paper introduce a high speed sensing, highly parallel processing image sensor system comprising a 3-D stacked image sensor with extremely fast signal sensing and processing speed and a 3-D stacked microprocessor with a self-test and self-repair function for autonomous driving assist fabricated by 3-D heterogeneous integration technologies.

Design of a Time-Multiplexing CNN Chip (시다중처리 셀룰러 신경망 칩설계)

  • 박병일;정금섭;전흥우;신경욱
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.4 no.2
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    • pp.505-516
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    • 2000
  • Cellular Neural Networks(CNN) is a nonlinear information-processing system that has a locally connected characteristic and is widely used in the real-time high speed image processing. In this paper, a practical system approach of time-multiplexing CNN implementations suitable for processing large and complex images using small CNN arrays is presented and $6\times6$ CNN hardware is designed for the processing of a large image. While previous implementations are mostly suitable for black and white applications because of the thresholded outputs, our approach is especially suitable for applications in gray image processing due to the analog nature of the state node. CNN chip is designed using a 0.65${\mu}{\textrm}{m}$ 2P2M(double poly, double metal) N-Well CMOS process technology. It contains about 15,400 devices on an area of about $1.85\times1.75$ md. The designed $6\times6$ CNN is tested for the edge detection of a large image input and it's performance is verified.

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Range-Scaled 14b 30 MS/s Pipeline-SAR Composite ADC for High-Performance CMOS Image Sensors

  • Park, Jun-Sang;Jeong, Jong-Min;An, Tai-Ji;Ahn, Gil-Cho;Lee, Seung-Hoon
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.16 no.1
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    • pp.70-79
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    • 2016
  • This paper proposes a low-power range-scaled 14b 30 MS/s pipeline-SAR composite ADC for high-performance CIS applications. The SAR ADC is employed in the first stage to alleviate a sampling-time mismatch as observed in the conventional SHA-free architecture. A range-scaling technique processes a wide input range of 3.0VP-P without thick-gate-oxide transistors under a 1.8 V supply voltage. The first- and second-stage MDACs share a single amplifier to reduce power consumption and chip area. Moreover, two separate reference voltage drivers for the first-stage SAR ADC and the remaining pipeline stages reduce a reference voltage disturbance caused by the high-speed switching noise from the SAR ADC. The measured DNL and INL of the prototype ADC in a $0.18{\mu}m$ CMOS are within 0.88 LSB and 3.28 LSB, respectively. The ADC shows a maximum SNDR of 65.4 dB and SFDR of 78.9 dB at 30 MS/s, respectively. The ADC with an active die area of $1.43mm^2$ consumes 20.5 mW at a 1.8 V supply voltage and 30 MS/s, which corresponds to a figure-of-merit (FOM) of 0.45 pJ/conversion-step.

A Stereo Audio DAC with Asymmetric PWM Power Amplifier (비대칭 펄스 폭 변조 파워-앰프를 갖는 스테레오 오디오 디지털-아날로그 변환기)

  • Lee, Yong-Hee;Jun, Young-Hyun;Kong, Bai-Sun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.7
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    • pp.44-51
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    • 2008
  • A stereo audio digital-to-analog converter (DAC) with a power amplifier using asymmetric pulse-width modulation (PWM) is presented. To adopt class-D amplifier mainly used in high-power audio appliances for head-phones application, this work analyzes the noise caused by the inter-channel interference during the integration and optimizes the design of the sigma-delta modulator to decrease the performance degradation caused by the noise. The asymmetric PWM is implemented to reduce switching noise and power loss generated from the power amplifier. This proposed architecture is fabricated in 0.13-mm CMOS technology. The proposed audio DAC including the power amplifier with single-ended output achieves a dynamic range (DR) of 95-dB dissipating 4.4-mW.

Design of Transmitter for UWB Chaotic-OOK Communications (UWB Chaotic-OOK 통신을 위한 송신기 설계)

  • Jeong, Moo-Il;Kong, Hyo-Jin;Lee, Chang-Suk
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.19 no.3
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    • pp.384-390
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    • 2008
  • Chaotic OOK modulation method can be used in LDR(Low Data Rate) UWB systems. In this paper, UWB chaotic-OOK transmitter system is designed and verified using TSMC 0.18 um CMOS process. A transmitter system is composed of Quasi-chaotic signal generator, OOK Modulator, and driving amplifier. The traditional chaotic signal generators using analog feedback method is weak to process variation. In order to solve this problem, a quasi-chaotic signal generator using digital feedback technique is get wide band signal and OOK Modulator using T-type switching structure is used to enhance the isolation characteristic. A driving amplifier has differential to single structure to avoid an external balun for low cost communication. The measured output power spectrum of the transmitter meet the FCC regulation and the result of the modulation test at data rate of 20 Kbps, 200 Kbps, 2 Mbps, and 10 Mbps is conformed to LDR UWB system. It is shown that the transmitter in this paper can be used for the UWB chaotic-OOK system.

Design and implementation of comb filter for multi-channel, 24bit delta-sigma ADC (다채널 24비트 델타시그마 ADC 용 콤필터 설계 및 구현)

  • Hong, Heedong;Park, Sangbong
    • The Journal of the Convergence on Culture Technology
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    • v.6 no.3
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    • pp.427-430
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    • 2020
  • The multi-channel analog signal to digital signal conversion is increasing in the field of IoT and medical measurement equipments. It has chip area and power consumption constraints to use a few single or 2_channel ADC for multi_channel application. This paper described to design and implement a proposed comb filter for multi-channel, 24bit ADC. The function of proposed comb filter is verified by matlab simulation and the FPGA test board. It was fabricated using SK Hynix 0.35㎛ CMOS standard process. The performance and chip size is compared with the existing design method that uses integrator/differentiator and FIR construction. The proposed comb filter is expected to use the IoT product and medical measurement equipments that require multi-channel, low power consumption and small hardware size.