• 한국정보디스플레이학회:학술대회논문집
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• 2000.01a
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• pp.15-16
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• 2000

The gate bias stress effect of the hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) with a $SiN_x/BCB$ gate insulator have been studied. The gate planarization was carried out by spin-coating of BCB (benzocyclobutene) on Cr gates. The BCB exhibits charge trappings during a high gate bias, but the stability of the TFT is the same as conventional one when it is between -25 V and +25 V. The charge trap density in the BCB increases with its thickness.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.1
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• pp.1-4
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• 2008

The electrical characteristics of polycrystalline silicon (poly-Si) thin film transistor (TFT) crystallized by excimer laser annealing (ELA) method were evaluated, The polycrystalline silicon thin-film transistor (poly-Si TFT) has higher electric field-effect-mobility and larger drivability than the amorphous silicon TFT. However, to poly-Si TFT's using conventional processes, the temperature must be very high. For this reason, an amorphous silicon film on a buried oxide was crystallized by annealing with a KrF excimer laser (248 nm)to fabricate a poly-Si film at low temperature. Then, High permittivity $HfO_2$ of 20 nm as the gate-insulator was deposited by atomic layer deposition (ALD) to low temperature process. In addition, the solid phase crystallization (SPC) was compared to the ELA method as a crystallization technique of amorphous-silicon film. As a result, the crystallinity and surface roughness of poly-Si crystallized by ELA method was superior to the SPC method. Also, we obtained excellent device characteristics from the Poly-Si TFT fabricated by the ELA crystallization method.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1701-1703
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• 2006

Here we describe a novel driving scheme in the form of negative AC bias stress (NAC) to compensate shift in the threshold voltage for hydrogenated amorphous silicon (${\alpha}$-Si:H) thin film transistor (TFT) for AMOLED applications. This scheme preserves the threshold voltage shift of ${\alpha}$-Si:H TFT for infinitely long duration of time(>30,000 hours) and thereby overall performance, without using any additional TFTs for compensation. We briefly describe about the possible driving schemes in order to implement for real time AMOLED applications. We attribute most of the results based on concept of plugging holes and electrons across the interface of the gate insulator in a controlled manner.

• Proceedings of the Korean Vacuum Society Conference
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• 2000.02a
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• pp.186-186
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• 2000

After LeComber et al. reported the first amorphous hydrogenated silicon (a-Si: H) TFT, many laboratories started the development of an active matrix LCDs using a-Si:H TFTs formed on glass substrate. With increasing the display area and pixel density of TFT-LCD, however, high mobility TFTs are required for pixel driver of TF-LCD in order to shorten the charging time of the pixel electrodes. The most important of these drawbacks is a-Si's electron mobiliy, which is the speed at which electrons can move through each transistor. The problem of low carier mobility for the a-Si:H TFTs can be overcome by introducing polycrystalline silicon (poly-Si) thin film instead of a-Si:H as a semiconductor layer of TFTs. Therefore, poly-Si has gained increasing interest and has been investigated by many researchers. Recnetly, fabrication of such poly-Si TFT-LCD panels with VGA pixel size and monolithic drivers has been reported, . Especially, fabricating poly-Si TFTs at a temperature mach lower than the strain point of glass is needed in order to have high mobility TFTs on large-size glass substrate, and the monolithic drivers will reduce the cost of TFT-LCDs. The conventional methods to fabricate poly-Si films are low pressure chemical vapor deposition (LPCVD0 as well as solid phase crystallization (SPC), pulsed rapid thermal annealing(PRTA), and eximer laser annealing (ELA). However, these methods have some disadvantages such as high deposition temperature over $600^{\circ}C$, small grain size (<50nm), poor crystallinity, and high grain boundary states. Therefore the low temperature and large area processes using a cheap glass substrate are impossible because of high temperature process. In this study, therefore, we have deposited poly-Si thin films on si(100) and glass substrates at growth temperature of below 40$0^{\circ}C$ using newly developed high rate magnetron sputtering method. To improve the sputtering yield and the growth rate, a high power (10~30 W/cm2) sputtering source with unbalanced magnetron and Si ion extraction grid was designed and constructed based on the results of computer simulation. The maximum deposition rate could be reached to be 0.35$\mu$m/min due to a high ion bombardment. This is 5 times higher than that of conventional sputtering method, and the sputtering yield was also increased up to 80%. The best film was obtained on Si(100) using Si ion extraction grid under 9.0$\times$10-3Torr of working pressure and 11 W/cm2 of the target power density. The electron mobility of the poly-si film grown on Si(100) at 40$0^{\circ}C$ with ion extraction grid shows 96 cm2/V sec. During sputtering, moreover, the characteristics of si source were also analyzed with in situ Langmuir probe method and optical emission spectroscopy.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.239-244
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• 2017

We experimentally investigate the physical mechanism for asymmetrical degradation in amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) under simultaneous gate and drain bias stresses. The transfer curves exhibit an asymmetrical negative shift after the application of gate-to-source ($V_{GS}$) and drain-to-source ($V_{DS}$) bias stresses of ($V_{GS}=24V$, $V_{DS}=15.9V$) and ($V_{GS}=22V$, $V_{DS}=20V$), but the asymmetrical degradation is more significant after the bias stress ($V_{GS}$, $V_{DS}$) of (22 V, 20 V) nevertheless the vertical electric field at the source is higher under the bias stress ($V_{GS}$, $V_{DS}$) of (24 V, 15.9 V) than (22 V, 20 V). By using the modified external load resistance method, we extract the source contact resistance ($R_S$) and the voltage drop at $R_S$ ($V_{S,\;drop}$) in the fabricated a-IGZO TFT under both bias stresses. A significantly higher RS and $V_{S,\;drop}$ are extracted under the bias stress ($V_{GS}$, $V_{DS}$) of (22 V, 20V) than (24 V, 15.9 V), which implies that the high horizontal electric field across the source contact due to the large voltage drop at the reverse biased Schottky junction is the dominant physical mechanism causing the asymmetrical degradation of a-IGZO TFTs under simultaneous gate and drain bias stresses.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.217-217
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• 2016

The amorphous InGaZnO (a-IGZO) is widely accepted as a promising channel material for thin-film transistor (TFT) applications owing to their outstanding electrical properties [1, 2]. However, a-IGZO TFTs have still suffered from their bias instability with illumination [1-4]. Up to now, many researchers have studied the sub-gap density of states (DOS) as the root cause of instability. It is well known that defect states can influence on the performances and stabilities of a-IGZO TFTs. The defects states should be closely related with the deposition condition, including sputtering power, and pressure. Nevertheless, it has not been reported how these defects are created during conventional RF magnetron sputtering. In general, during conventional RF magnetron sputtering process, negative oxygen ions (NOIs) can be generated by electron attachment in oxygen atom near target surface and then accelerated up to few hundreds eV by a self-bias; at this time, the high energy bombardment of NOIs induce defects in oxide thin films. Recently, we have reported that the properties of IGZO thin films are strongly related with effects of NOIs which are generated during the sputtering process [5]. From our previous results, the electrical characteristics and the chemical bonding states of a-IGZO thin films were depended with the bombardment energy of NOIs. And also, we suggest that the deep sub-gap states in a-IGZO as well as thin film properties would be influenced by the bombardment of high energetic NOIs during the sputtering process.In this study, we will introduce our novel technology named as Magnetic Field Shielded Sputtering (MFSS) process to prevent the NOIs bombardment effects and present how much to be improved the properties of a-IGZO thin film by this new deposition method. We deposited a-IGZO thin films by MFSS on SiO2/p-Si and glass substrate at various process conditions, after which we investigated the morphology, optical and electrical properties of the a-IGZO thin films.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2018.06a
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• pp.55-55
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• 2018

Recently, amorphous oxides such as InGaZnO (IGZO) and InZnO (IZO) as a channel layer of an oxide TFT have been attracted by advantages such as high mobility, good uniformity, and high transparency. In order to apply such an amorphous oxide TFTs to a display, the stability in various environments must be ensured. In the InGaZnO which has been studied in the past, Ga elements act as a suppressor of oxygen vacancy and result in a decreased mobility at the same time. Previous studies have been showed that the InZnO, which does not contain Ga, can achieve high mobility, but has relatively poor stability under various instability environments. In this study, the TFTs using $IZO/Al_2O_3$ double layer structure were studied. The introduction of an $Al_2O_3$ interlayer between source/drain and channel causes superior electrical characteristics and electrical stability as well as reduced contact resistance with optimally perfect ohmic contact. For the IZO and $Al_2O_3$ bilayer structures, the IZO 30nm IZO channels were prepared at $Ar:O_2=30:1$ by sputtering and the $Al_2O_3$ interlayer were depostied with various thickness by ALD at $150^{\circ}C$. The optimal sample exhibits considerably good TFT performance with $V_{th}$ of -3.3V and field effect mobility of $19.25cm^2/Vs$, and reduced $V_{th}$ shift under positive bias stress stability, compared to conventional IZO TFT. The enhanced TFT performances are closely related to the nice ohmic contact properties coming from the defect passivation of the IZO surface inducing charge traps, and we will provide the detail mechanism and model via electrical analysis and transmission line method.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.5
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• pp.1013-1019
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• 2007

Amorphous silicon and silicon-nitride films were deposited using plasma-enhanced chemical vapor deposition (PECVD) method at $150^{\circ}C$. As fraction of $H_2$ in source gas was increased, characteristics of low-temperature silicon-nitride films approached those of conventional high-temperature films; the refractive index approached 1.9 and the ratio of nitrogen-hydrogen bonds to silicon-hydrogen bonds increased. And also, as fraction of $H_2$ in source gas was increased, characteristics of low-temperature silicon films approached those of conventional high-temperature films; refractive index and optical band gap approached 4.2 and 1.8 eV, and $[Si-H]/([Si-H]+[Si-H_2])$ increased. Lower RF power and process-pressure made the amorphous silicon films to be better properties. Increase of $H_2$ ratio seemed as the common factor to get reliable amorphous silicon and silicon-nitride films for thin-film-transistors (TFTs) at low temperature.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.163-163
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• 2015

The effect of nematic liquid crystal(5CB-4-Cyano-4'-pentylbiphenyl) on the amorphous indium gallium zinc oxide thin film transistors(a-IGZO TFTs) was investigated. Through dropping the 5CB on the a-IGZO TFT's channel layer which is deposited by RF-magnetron sputtering, properties of a-IGZO TFTs was dramatically improved. When drain bias was induced, 5CB molecules were oriented by Freedericksz transition generating positive charges to one side of dipoles. From increment of the capacitance by orientation of liquid crystals, the drain current was increased, and we analyzed these phenomena mathematically by using MOSFET model. Transfer characteristic showed improvement such as decreasing of subthreshold slope(SS) value 0.4 to 0.2 and 0.45 to 0.25 at linear region and saturation region, respectively. Furthermore, in positive bias system(PBS), prevention effect for electron trapping by 5CB liquid crystal dipoles was observed, which showing decrease of threshold voltage shift [(${\delta}V$]_TH) when induced +20V for 1~1000sec at the gate electrode.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.200-200
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• 2003

Polycrystalline Si(polysilicon) TFTs have opened a way for the next generation of display devices, due to their higher mobility of charge carriers relative to a-Si TFTs. The polysilicon W applications extend from the current Liquid Crystal Displays to the next generation Organic Light Emitting Diodes (OLED) displays. In particular, the OLED devices require a stricter control of properties of gate oxide layer, polysilicon layer, and their interface. The polysilicon layer is generally obtained by annealing thin film a-Si layer using techniques such as solid phase crystallization and excimer laser annealing. Typically laser-crystallized Si films have grain sizes of less than 1 micron, and their electrical/dielectric properties are strongly affected by the presence of grain boundaries. Impedance spectroscopy allows the frequency-dependent measurement of impedance and can be applied to inteface-controlled materials, resolving the respective contributions of grain boundaries, interfaces, and/or surface. Impedance spectroscopy was applied to laser-annealed Si thin films, using the electrodes which are designed specially for thin films. In order to understand the effect of grain size on physical properties, the amorphous Si was exposed to different laser energy densities, thereby varying the grain size of the resulting films. The microstructural characterization was carried out to accompany the electrical/dielectric properties obtained using the impedance spectroscopy, The correlation will be made between Si grain size and the corresponding electrical/dielectric properties. The ramifications will be discussed in conjunction with active-matrix thin film transistors for Active Matrix OLED.