• 한국신재생에너지학회:학술대회논문집
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• 2011.05a
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• pp.115.1-115.1
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• 2011

최근 기본적인 pin 구조의 박막 cell 에서 i layer를 최적화 시키는 방안으로 double layer 구조가 많이 연구되고 있다. 본 연구에서는 ASA(Advanced Semicon ductor Analysis) simulation을 이용하여 i-double layer 최적화에 대한 연구를 진행해 보았다. 두께 150/150nm의 i double layer의 band gap 가변을 한 simulation 결과를 보았을 때, p쪽의 band gap이 상승하면서 intrinsic layer 내의 field가 증가하여 recombination center가 감소하였으나 FF의 감소가 있었다. n쪽의 band gap을 상승 시켰을때 n/i 쪽 field 증가로 Voc가 상승되어 초기 효율이 증가하였으나 intrinsic layer내의 field가 감소하여 recombination center가 오히려 증가하였다. 결과적으로 electric field와 효율을 동시에 고려했을 때 두께 300nm, 1.75의 band gap을 가지는 single layer 보다 150/150nm두께에 1.8/1.7 또는 1.8/1.75의 bandgap을 가지는 double layer를 사용하였을 때 보다 높은 효율을 얻을 수 있었다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.10a
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• pp.475-479
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• 2000

The box capacitor structure with H5G-Si described here reliably achieves a cell capacitance of 28fF with a cell area of a 0.482f${\mu}{\textrm}{m}$$^2$ for 128Mbit DRAM. An H5G-Si formation technology with seeding method, which employs Si$_2$H$_{6}$ molecule irradiation and annealing, was applied for realizing 64Mbit and larger DRAMS. By using this technique, grain size controlled H5G-Si can be fabricated on in-situ phosphorous doped amorphous silicon electrodes. The HSG-Si fabrication technology achieves twice the storage capacitance with high reliability for the stacked capacitors.s.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1995.11a
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• pp.118-121
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• 1995

Fabrication and a new analytical expression for the capacitance characteristics of hydrogenerated amorphous silicon thin film transistors(a-Si:H TFTs) is presented and experimentally verified. The results show that the experimental capacitance characteristics are easily measeured. Measured transfer and DC output characteristic curves of a-Si:H TFT are similar to those of the standard MOSFET-IC. The capacitances on bias voltages are in good agreement with experimental data. This capacitance characteristics is suitable for incorporation into a circuit simulator and can be used for computer-aided design of a-Si thin film transistor integrated circuits.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1997.04a
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• pp.168-171
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• 1997

TFT2DS was developed to provide the usefulness as an analytic and design tool. The static characteristics of a-Si:H TFTs demonstrated a good agreement between simulated and measured data. This paper shows that TFT2DS can optimize the physical parameters of a-Si:H through sensitivity simulations and compute the static characteristics of a-Si:H TFTs. Moreover, through the sensitivity study of the parameters, it is shown that the optimizations of both the physical parameters of a-Si:H and the parameters of a-Si:H deposition, which must be inter-related, might be possibl.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.8
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• pp.34-41
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• 1993

Effect of high temperature annealing conditions on Ta$_{2}O_{5}$ thin films was investigated. Ta$_{2}O_{5}$ thin films were deposited on P-type silicon substrates by plasma-enhanced chemical vapor deposition (PECVD) using tantalum ethylate. Ta(C$_{2}H_{5}O)_{5}$, and nitrous oxide. N$_{2}$O. The microstructure changed from amorphous to polycrystalline above 700.deg. C annealing temperature. The refractive index, dielectric onstant and leakage current of the film increased as annealing temperature increased. However, annealing in oxygen ambient reduced leakage currents and dielectric constant due to the formation of interfacial SiO$_{2}$ layer. By optimizing annealing temperature and ambient, leakage current lower than 10$^{-8}$ A/cm$^{2}$ and maximum capacitance of 9 fF/${\mu}m^{2}$ could be obtained.

• Korean Journal of Crystallography
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• v.14 no.2
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• pp.56-61
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• 2003

Nanocrystalline hydrogenated silicon (nc-Si : H) thin films were deposited at room temperature by plasma enhanced chemical vapor deposition (PECVD): a mixture of SiH₄ and H₂ gas was introduced into the evacuated reaction chamber. When the H₂ gas flow rate was low, the density of Si-H₃ bonds was high in the films. On the other hand, when the H₂ gas flow rate was high, e.g., 100 sccm, a large number of Si-H bonds contributed to the passivation of the surface of the large volume of Si nanocrystallites. The relative fraction of the Si-H₃ and Si-H₂ bonds in the amorphous matrix varied sensitively with the H₂ gas flow rate. The variation was associated with the change in the intensity as well as the wavelength of the main PL peaks, indicating the change in the total volume as well as the size of the Si nanocrystallites in the films.

• Journal of the Korean Ceramic Society
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• v.32 no.6
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• pp.710-718
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• 1995

The new forming method, Pressureless Powder Packing Forming Method was applied to the manufacturing of reaction sintered SiC. After the experiments of vibratory powder packing and binder infiltration, the abrasive SiC powder of which mean size is 45${\mu}{\textrm}{m}$ was selected to this forming method. Uniform green bodies with porosity of 45% and narrow pore size distribution could be formed by this new forming method. Also, complex or varied cross-sectional shapes could be easily manufactured through the silicone rubber mould used in this forming method. Maximum 15 wt% amorphous carbon was penetrated into green body by multi impregnation-carbonization cycles. And reaction-bonded SiC was manufactured by infiltration of SiC-carbon shaped bodies with liquid silicon.

• Journal of Information Display
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• v.6 no.3
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• pp.12-17
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• 2005

The need for low cost, flexible, thin film transistor (TFT) display backplanes has focused attention on new processing techniques and materials. We report the development of TFT backplane technology based entirely on jet-printing, using a combination of additive and subtractive processing, to print active materials or etch masks. The technique eliminates the use of photolithography and has the potential to reduce the array manufacturing cost. The printing technique is demonstrated with both amorphous silicon and polymer semiconductor TFT arrays, and we show results of small prototype displays.

• Journal of Information Display
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• v.7 no.1
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• pp.35-40
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• 2006

Organic light-emitting diode (OLED) display panel using the charge-pump (CP) pixel addressing scheme was fabricated, and the results show that it is applicable for information display. A CP-OLED panel with 64 ${\times}$ 64 pixels consisting of thin-film capacitors and amorphous silicon Schottky diodes was fabricated using conventional thin-film processes. The pixel drive circuit passes electrical current into the OLED cell during most of the frame period as in the thin-film transistor (TFT)-based active-matrix (AM) OLED displays. In this study, the panel was operated at a voltage level of below 4 V, and this operation voltage can be reduced by eliminating the overlap capacitance between the column bus line and the common electrode.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.1272-1275
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• 2008

We present the development of dry etch process for the liquid crystal display (LCD) fabrication using a dielectric barrier discharge (DBD) system at atmospheric pressure. In this experimental work, the dry etch characteristics and the electrical properties of thin film transistor are evaluated by using the scanning electron microscopy and electric probe, and TFT-LCD panel ($300\;mm\;{\times}\;400\;mm$) is manufactured with the application of the amorphous silicon etch step in the 4 mask and 5 mask processes.