• Journal of the Korea Society of Computer and Information
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• v.17 no.11
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• pp.1-10
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• 2012

In this paper, the extension of the addressing mode in the 16-bit Thumb instruction set architecture is proposed to improve the performance of 16-bit Thumb code. The key idea of the proposed approach is the introduction of new addressing modes for more frequent instructions by using the saved bits from the reduction of the register fields in less frequently used instructions. The proposed approach adopts efficient addressing modes from the 32-bit ARM architecture, which is the superset of the 16-bit Thumb architecture. To speed up access to a data list, scaled register offset addressing mode and post-indexed addressing mode are introduced for load and store instructions. Experiments show that the proposed approach improves performance by an average of 8.5% when compared to the conventional approach.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.1105-1108
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• 1999

In this paper, we propose a new addressing mode, which can be used for programmable image processor to perform image- processing algorithms effectively. Conventional addressing modes are suitable for one-dimensional data processing such as voice, but the proposed addressing mode consider two-dimensional characteristics of image data. The proposed instruction for two-dimensional addressing requires two operands to specify a pixel and doesn't require any change of memory architecture. Combining several instructions to load a pixel-data from an external memory to a register, the proposed instruction reduces code size so that satisfy hish performance and low power requirements of image processor. In addition, it uses inherent two-dimensional characteristics of image data and offers user-friendly instruction to assembler programmer.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.38 no.5
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• pp.486-497
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• 2001

In this paper, we propose a new addressing mode, which can be used for programmable image processor to perform image-processing algorithms effectively. Conventional addressing modes are suitable for one-dimensional data processing such as voice, but the proposed addressing mode consider two-dimensional characteristics of image data. The proposed instruction for two-dimensional addressing requires two operands to specify a pixel and doesn't require any change of memory architecture. The proposed two-dimensional addressing mode for image processor has the following advantages. The proposed instruction combines several instructions to load a pixel data from an external memory to a register. Hence, the proposed instruction reduces required code size so that it satisfies high performance and low power requirements of image processor. In addition, it uses inherent two-dimensional characteristics of image data and offers user-friendly instruction to assembler programmer The proposed two-dimensional addressing mode is applicable to DSP, media processor, graphic device, and so on. In this paper, we propose a new concept of two-dimensional addressing mode and an efficient hardware implementation method of it.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.12
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• pp.2211-2217
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• 2016

The Locator/Identifier Separation Protocol (LISP) is a new routing architecture that implements a new semantic for IP addressing. It enables the separation of IP addresses into two new numbering spaces: Endpoint Identifiers (EIDs) and Routing Locators (RLOCs). This approach will solve the issue of rapid growth of the Internet's DFZ (default-free zone). In this paper, we propose an algorithm called the Propagated-Mode Mapping System to improve the map request process of LISP-DDT.

• The KIPS Transactions:PartA
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• v.16A no.6
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• pp.443-452
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• 2009

Although 32-bit architectures are becoming the norm for modern microprocessors, 16-bit ones are still employed by many low-end processors, for which small size and low power consumption are of high priority. However, 16-bit architectures have a critical disadvantage for embedded processors that they do not provide enough encoding space to add special instructions coined for certain applications. To overcome this, many existing architectures adopt non-orthogonal, irregular instruction sets to accommodate a variety of unusual addressing modes. In general, these non-orthogonal architectures are regarded compiler-unfriendly as they tend to requires extremely sophisticated compiler techniques for optimal code generation. To address this issue, we proposed a compiler-friendly processor with a new addressing mode, called the dynamic implied addressing mode(DIAM). In this paper, we will demonstrate that the DIAM provides more encoding space for our 16-bit processor so that we are able to support more instructions specially customized for our applications. And we will explain the advanced architecture which has improved performance. In our experiment, the proposed architecture shows 11.6% performance increase on average, as compared to the basic architecture.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.706-709
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• 2003

We made an optimization effort on driving waveforms for the Quantized Memory Addressing (QMA) in selective write mode of operation. It was necessary to add long ramp type erase pulses after the total write pulse and the sustain period to obtain stable intermediate luminance discharges. Furthermore, fast rising ramp type total write as well as two step addressing scheme were adopted for better discharge stability.

• Journal of Aerospace System Engineering
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• v.2 no.3
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• pp.33-39
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• 2008

VDL Mode 2 is one of air-to-ground VHF digital data link technologies. The VDL Mode 2 system is designed to be an air-to-ground subnetwork of the Aeronautical Telecommunication Network (ATN) using the AM(R)S band and it is organized according to the Open System Interconnection (OSI) model (defined by ISO). It can be used in ATS Applications especially for ATC communication such as CPDLC and ADS as well. And It is expected VDL Mode 2 replaces ACARS(Aircraft Communications Addressing and Reporting System) which has broadly been used for over 20 years. This paper presents the result of design of operational test equipments for the validation of VDL Mode 2 system under development in KARI.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.18 no.3
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• pp.15-19
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• 2004

We presented the holographic memory system using a multi-mode optical fiber. In this system, we multiplexed multiple holograms using the lights from multi-mode optical fibers as reference beams. The proposed system has two degrees of multiplexing freedom: speckle pattern of light coming from multi-mode fiber and spatial location of multi-mode fibers. Therefore, the data addressing in the system can be performed by mode and spatial multiplexings.

• Proceedings of the Earthquake Engineering Society of Korea Conference
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• 2005.03a
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• pp.153-160
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• 2005

A new nonlinear static analysis method, Effective Modal Pushover Analysis (EMPA) which can evaluate earthquake responses such as story drift and plastic rotation of plastic hinges addressing higher mode effects was developed. Unlike existing nonlinear static procedure based on properties of fundamental vibration mode, the EMPA performs nonlinear static analysis using multiple effective modes constructed by direct combination of natural vibration modes. Therefore higher mode effects can be efficiently considered. In the present study, procedures of the EPMA evaluating inelastic earthquake responese were established and the results were verified by nonlinear time history analysis. The EMPA can be applied to seismic evaluation of high-rise buildings and irregular buildings where higher mode effects become conspicuous.

• The KIPS Transactions:PartA
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• v.12A no.3 s.93
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• pp.263-272
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• 2005

The addressing mode for data is performed by the software in yon Neumann-concept(SISD) computer a priori without hardware design of an address counter for operands. Therefore, in the addressing mode for the vector the corresponding variables as much as the number of the elements should be specified and used also in the software method. This is because not for operand but only for an instructions, quasi PC(program counter) is designed in hardware physically. A vector has a characteristic of a structural dimension. In this paper we propose to design a hardware unit physically external to the CPU for addressing only the elements of a vector unit with the structure and dimension. Because of the high speed performance for a vector processing it should be designed in the SIMD pipeline mechanics. The proposed mechanics is evaluated through a simulation. Our result shows $12\%$ to $30\%$ performance enhancement over CRAY architecture under the same hardware consideration(processing unit).