• 한국진공학회지
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• 제20권1호
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• pp.7-13
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• 2011

자기조립화된 Fe/Au 이중층 위에 $L1_0$형 구조를 갖는 FePd 나노 점을 성공적으로 제작하였다. AFM를 이용하여 초기에 편평한 Fe/Au 이중층 박막이 온도가 증가함에 따라서 응집되어 나노 점 구조로 변형되는 것을 확인하였다. 또한 형성된 이중층위에 FePd 다층막을 $300^{\circ}C$, $350^{\circ}C$, $400^{\circ}C$, $450^{\circ}C$에서 각각 증착하였다. 초격자 구조를 갖는 FePd 다층막의 표면형상은 응집현상에 의하여 자기조립화된 이중층의 형상과 유사하였다. XRD 측정결과, $350^{\circ}C$ 이상에서 열처리된 FePd 다층막은 $L1_0$형 구조를 갖는다는 것을 확인하였다. 그리고 박막두께에 따른 XPS 측정결과는 전체 박막의 화학적 조성이 증착순서와 일치하는 것을 보여주었다. 결과적으로 추가적인 식각공정 없이 화학적으로 규칙화된 FePd 초격자 나노 점의 제작에 성공하였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• 대한소아치과학회지
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• 제45권4호
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• pp.436-444
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• 2018

이 연구의 목적은 최근 새로 소개된 3-in-1 자가부식, 자가접착 유동성 복합레진의 유치 법랑질과 상아질에 대한 결합력을 기존의 접착 시스템들과 비교 평가하기 위함이다. 110개의 발치된 건전한 유전치를 상아질과 법랑질, 그리고 접착 시스템에 따라 11개의 군으로 나눴다. 연구재료로 Scotchbond Multi-Purpose Plus, Single bond 2, Clearfil SE Bond, All-Bond Universal, Constic을 사용하여 전단결합강도를 평가하였다. 3-in-1 자가부식, 자가접착 유동성 복합레진은 상아질과 법랑질 연구에서 모두 가장 낮은 전단결합강도를 나타냈지만 몇몇 접착 시스템과는 유의한 차이를 나타내지 않아 유치 수복에서 사용될 수 있을 것으로 생각되나 추가적인 연구가 필요할 것으로 여겨진다.