• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.887-890
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• 2003

High Speed data transmission over a long length of cable is limited due to the limited bandwidth of a cable which introduces ISI(Inter Symbol Interference). In order to compensate for the loss and phase dispersion in the cable, a pulse shaping in a transmitter and a line equalizer in receiver can be used. This paper presents a low-power and small-ana analog adaptive pulse shaping circuit and line equalizer, The design was fabricated in a 0.25${\mu}{\textrm}{m}$ mixed-signal CMOS process. The proposed pulse shaping circuit and equalizer operate at 400Mb/s on 50m STP(Shielded Twisted Pair) cable. It consumes 28.5${\mu}{\textrm}{m}$ with a 2.5-V power supply and occupies only 0.098 $\textrm{mm}^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.34-39
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• 2007

Serial links via backplane channels suffer from severe signal integrity problems which are normally caused by channel imperfections, such as flat loss, frequency-dependent loss, reflection, etc. Particularly, the frequency-dependent loss causes ISI(Inter-Symbol-Interference) at signal waveforms. Therefore, adaptive equalizing techniques have been exploited in many products to facilitate the ISI problem. In this paper, we present an analog adaptive equalizer circuit designed in a $0.18{\mu}m$ CMOS process. It achieves 10Gb/s data transmission through a long 34-inch backplane channel(or transmission line). The post-layout simulations demonstrate $8ps_{p-p}$ jitter with 10mW power dissipation. The core of the adaptive equalizer occupies the area of $0.56mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.119-124
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• 2008

Transimpedance amplifier(TIA) is the most significant element to determine the performance of the optical receiver, and thus the TIA must satisfy tile design requirements of high gain and wide bandwidth. In f)is paper, we propose a novel single chip optical receiver that exploits an analog adaptive equalizer and a limiting amplifier to enhance the gain and bandwidth performance, respectively. The proposed optical receiver is designed by using a $0.13{\mu}m$ CMOS process and its post-layout simulations show $120dB{\Omgea}$ transimpedance gain and 5.88GHz bandwidth. The chip core occupies the area of $0.088mm^2$, due to utilizing the negative impedance converter circuit rather than using on-chip passive inductors.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.11
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• pp.1034-1042
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• 2004

In this paper, as one of countermeasure techniques for a frequency selective fading, an adaptive analog slope equalizer(ASE) applicable to 64-QAM digital radio relay system is presented in terms of principle, implementation, and its performance. Also interference of cross-talk between I- and Q-channel caused by a fiequency selective lading has been analyzed by doing channel model in the baseband, which make it possible to derive the solution for implementing ASE in If-band. The effects of signal for the faded channel are investigated in the time and the frequency domains, respectively, with/without ASE. As system performance, it is shown that the signature is improved up to 6.2 dB at the edge of signal bandwidth for a given BER 10$\^$-3/.

• Journal of Korea Multimedia Society
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• v.12 no.3
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• pp.329-334
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• 2009

When an optical disc is being played. the pick-up converts light to analog signal at first. The analog signal is equalized for removing the inter-symbol interference and then the equalized analog signal is converted into the digital signal for extracting the synchronized data and clock signals. There are a lot of algorithms that minimize the BER in extracting the synchronized data and clock when high. density optical disc like BD is being played in low speed. But if the high-density optical disc is played in high speed, it is difficult to adopt the same extraction algorithm to data PLL and PRML architecture used in low speed application. It is because the signal with more than 800MHz should be processed in those architectures. Generally, in the 0.13-${\mu}m$ CMOS technology, it is necessary to have the high speed analog cores and lots of efforts to layout. In this paper, the parallel data PLL and PRML architecture, which enable to process in BD 8x speed of the maximum speed of the high-density optical disc as the extracting data and clock circuit, is proposed. Test results show that the proposed architecture is well operated without processing error at BD 8x speed.

• Proceedings of the Korea Committee for Ocean Resources and Engineering Conference
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• 2003.05a
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• pp.341-344
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• 2003

There communicates using tire supersonic waves in tire underwater, that is different from tire ground that use tire propagation. Because using Law frequency to come under tire waves, bandwidth that is able to communicate is very smaller that tire mobile communication of tire ground. Also, The channel environment changes rapidly in tire shallow underwater than tire ground. Due to such a reason, data transmission technic that is able to tire maximum application to restricted bandwidth and tire signal processing technics that is able to conquer tire rapid changes of tire channel environment are being used. Algorithm is used at tire application of these technic has a lot of tire calculating quantity. So this research reveals small bulk and equal performance using one DSP chip and then implements QPSK transmitter, that uses SHARC DSP of Analog Device company, for tire underwater supersonic waves communication rapidly decrease tire calculating quantity.